PLL1707

PLL1708

SLES065 – DECEMBER 2002

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11

Table 2. Sampling Frequencies

SAMPLING RATE

SAMPLING FREQUENCY (kHz)

Half sampling frequencies†

16

22.05

24

Standard sampling frequencies

32

44.1

48

Double sampling frequencies

64

88.2

96

† PLL1708 only

Table 3. Sampling Frequencies and System Clock Output Frequencies

SAMPLING FREQUENCY (kHz)

SAMPLING RATE

256 fS

SCKO2 (MHZ)

384 fS

SCKO3 (MHZ)

16†

Half

4.096

6.144

22.05†

Half

5.6448

8.4672

24†

Half

6.144

9.216

32

Standard

8.192

12.288

44.1

Standard

11.2896

16.9344

48

Standard

12.288

18.432

64

Double

16.384

24.576

88.2

Double

22.5792

33.8688

96

Double

24.576

36.864

† PLL1708 only

Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time from

sampling frequency change to SCKO settling is 300 ns maximum. Figure 10 illustrates SCKO transient timing in the

PLL1708.

SCKO0

SCKO1

300 ns

SCKO2

SCKO3

MS

Stable

Clock Transition Region

Stable

33.8688 , 36.864, or 24.576 MHz

1–2 Clocks of MCKO1, 2

Figure 10. System Clock Transient Timing

The delay time for hardware control to use SR, FS2, FS1, or CSEL is 150 ns maximum. Figure 11 illustrates SCKO transient

timing in the PLL1707. Clock transient timing is not synchronized with the SCKOs. External buffers are recommended on

all output clocks in order to avoid degrading the jitter performance of the PLL1707/8.