PCM1850

PCM1851

SLES108 − MARCH 2004

www.ti.com

5

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

Supply voltage: VCC

–0.3 V to 6.5 V

Supply voltage: VDD

–0.3 V to 4 V

Ground voltage differences: AGND, DGND

±0.1 V

Digital input voltage: LRCK, BCK, DOUT, OVER

–0.3 V to (VDD + 0.3 V) < 4 V

Digital input voltage: RST, SCKI, MS (ADR)(2), MC (SCL)(2), MD (SDA)(2), TEST0, TEST1

–0.3 V to 6.5 V

Analog input voltage: VINL1–6, VINR1–6

–3 V to (VCC + 3 V) < 9 V

Analog input voltage: MOUTL, MOUTR, VREF1, VREF2, VREFS

–0.3 V to (VCC + 0.3 V) < 6.5 V

Input current (any pins except supplies)

±10 mA

Ambient temperature under bias

–40

°C to 125°C

Storage temperature

–55

°C to 150°C

Junction temperature

150

°C

Lead temperature (soldering)

260

°C, 5 s

Package temperature (IR reflow, peak)

260

°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) PCM1850 (PCM1851)

ELECTRICAL CHARACTERISTICS

All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted

PARAMETER

TEST CONDITIONS

PCM1850PJT, PCM1851PJT

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUT/OUTPUT

DATA FORMAT

Audio data interface format

Left-justified, I2S, right-justified

Audio data bit length

16, 24

bits

Audio data format

MSB-first, 2s complement

fS

Sampling frequency

16

48

96

kHz

256 fS

4.096

12.288

24.576

System clock frequency

384 fS

6.144

18.432

36.864

MHz

System clock frequency

512 fS

8.192

24.576

49.152

MHz

768 fS

12.288

36.864

—

INPUT LOGIC

VIH (1)

2

VDD

VIL (1)

Input logic level

0

0.8

VDC

VIH (2) (3)

Input logic level

2

5.5

VDC

VIL (2) (3)

0

0.8

IIH (2)

VIN = VDD

±10

IIL (2)

Input logic current

VIN = 0

±10

A

IIH (1) (3)

Input logic current

VIN = VDD

65

100

µA

IIL (1) (3)

VIN = 0

±10

(1) Pins 1, 2: LRCK, BCK (In slave mode, Schmitt-trigger input, with 50-kΩ typical pulldown resistor)

(2) Pins 7, 31, 32: SCKI, MC/SCL (PCM1850/1851), MD/SDA (PCM1850/1851) (Schmitt-trigger input, 5-V tolerant)

(3) Pins 8–10, 30: TEST0, TEST1, RST, MS/ADR (PCM1850/1851) (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V tolerant)