LAN9252VSLASHML datasheet(208/329 Pages) MICROCHIP

208 / 329 page

LAN9252

DS00001909A-page 208

 2015 Microchip Technology Inc.

12.9.7.3

Management Interface Timing

The MII_MDIO and MII_MDC timing is follows:

12.10 LEDs

The device includes one run LED (RUNLED) and a link / activity LED per port (LINKACTLED[0:2]). The LED pin polar-

ity is determined based on the corresponding LED polarity strap. The pin outputs are open drain or open source.

Note:

The LED pins for Port 0 and Port 2 are not swapped based on the chip mode.

The EtherCAT Core configuration provides for direct control of the RUN LED via the RUN LED Override Register.

All LED outputs may be disabled (un-driven) by setting the LED_DIS bit in the Power Management Control Register

(PMT_CTRL).

12.11 EtherCAT CSR and Process Data RAM Access

The EtherCAT CSRs provide register level access to the various parameters of the EtherCAT Core. EtherCAT related

registers can be classified into two main categories based upon their method of access: direct and indirect.

The directly accessible EtherCAT registers are part of the main system CSRs and are detailed in Section 12.13, "Eth-

erCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214. These registers provide

data/command registers (for access to the indirect EtherCAT Core registers).

The indirectly accessible EtherCAT Core registers reside within the EtherCAT Core and must be accessed indirectly via

the EtherCAT CSR Interface Data Register (ECAT_CSR_DATA) and EtherCAT CSR Interface Command Register

(ECAT_CSR_CMD). The indirectly accessible EtherCAT Core CSRs provide full access to the many configurable

parameters of the EtherCAT Core. The indirectly accessible EtherCAT Core CSRs are accessed at address 0h through

0FFFh and are detailed in Section 12.14, "EtherCAT Core CSR Registers (Indirectly Addressable)," on page 223.

FIGURE 12-9:

MANAGEMENT ACCESS TIMING

TABLE 12-6:

MANAGEMENT ACCESS TIMING VALUES

Symbol

Description

Min

Max

Units

Notes

tclkp

MII_MDC period

400

tclkh

MII_MDC high time

180 (90%)

tclkl

MII_MDC low time

180 (90%)

tval

MII_MDIO output valid from rising edge of MII_MDC

250

tohold

MII_MDIO output hold from rising edge of MII_MDC

150

tsu

MII_MDIO input setup time to rising edge of MII_MDC

tihold

MII_MDIO input hold time after rising edge of MII_MDC

MII_MDC

MII_MDIO

tclkh

tclkl

tclkp

tohold

MII_MDIO

tsu tihold

(Data-Out)

(Data-In)

tohold

tval

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