LAN9252SLASHML datasheet(305/329 Pages) MICROCHIP

305 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 305

LAN9252

17.0

JTAG

17.1

JTAG

A IEEE 1149.1 compliant TAP Controller supports boundary scan and various test modes.

The device includes an integrated JTAG boundary-scan test port for board-level testing. The interface consists of four

pins (TDO, TDI, TCK and TMS) and includes a state machine, data register array, and an instruction register. The JTAG

pins are described in Table 3-14, “JTAG Pin Descriptions,” on page 28. The JTAG interface conforms to the IEEE Stan-

dard 1149.1 - 2001 Standard Test Access Port (TAP) and Boundary-Scan Architecture.

All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI are clocked into

the test logic on the rising edge of TCK, while the output signal TDO is clocked on the falling edge.

JTAG pins are multiplexed with the GPIO/LED and EEPROM pins. The JTAG functionality is selected when the TEST-

MODE pin is asserted.

The implemented IEEE 1149.1 instructions and their op codes are shown in Table 17-1.

Note:

The JTAG device ID is 00101445h

Note:

All digital I/O pins support IEEE 1149.1 operation. Analog pins and the OSCI / OSCO pins do not support

IEEE 1149.1 operation.

TABLE 17-1:

IEEE 1149.1 OP CODES

INSTRUCTION

OP CODE

COMMENT

BYPASS 0

16'h0000

Mandatory Instruction

BYPASS 1

16'hFFFF

Mandatory Instruction

SAMPLE/PRELOAD

16'hFFF8

Mandatory Instruction

EXTEST

16'hFFE8

Mandatory Instruction

CLAMP

16'hFFEF

Optional Instruction

ID_CODE

16'hFFFE

Optional Instruction

HIGHZ

16'hFFCF

Optional Instruction

INT_DR_SEL

16'hFFFD

Private Instruction

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