LAN9252SLASHML datasheet(303/329 Pages) MICROCHIP

номер детали	LAN9252/ML

подробное описание детали	2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

PDF	329 Pages

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производитель	MICROCHIP [Microchip Technology]

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DS00001909A-page 303

LAN9252

16.1.2

BYTE ORDER TEST REGISTER (BYTE_TEST)

This read-only register can be used to determine the byte ordering of the current configuration. Byte ordering is a func-

tion of the host data bus width and endianess. Refer to Section 9.0, "Host Bus Interface," on page 62 for additional infor-

mation on byte ordering.

The BYTE_TEST register can optionally be used as a dummy read register when assuring minimum write-to-read or

read-to-read timing. Refer to Section 9.0, "Host Bus Interface," on page 62 for additional information.

For host interfaces that are disabled during the reset state, the BYTE_TEST register can be used to determine when

the device has exited the reset state.

Note:

This register can be read while the device is in the reset or not ready / power savings states without leaving

the host interface in an intermediate state. If the host interface is in a reset state, returned data may be

invalid. However, during reset, the returned data will not match the normal valid data pattern.

Note:

It is not necessary to read all fours BYTEs of this register. DWORD access rules do not apply to this register.

Offset:

064h

Size:

32 bits

Bits

Description

Type

Default

31:0

Byte Test (BYTE_TEST)

This field reflects the current byte ordering

87654321h

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