LAN9252SLASHML datasheet(198/329 Pages) MICROCHIP

198 / 329 page

LAN9252

DS00001909A-page 198

 2015 Microchip Technology Inc.

12.3

PDI Selection and Configuration

The Process Data Interface (PDI) used by the device is indicated via the PDI Control Register. The available PDIs are:

• 04h: Digital I/O PDI

• 80h-8Dh: Host Interface PDI (SPI, HBI Multiplexed/Indexed 1/2 Phase 8/16-bit)

Note:

The PDI Control Register can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configurable

Registers," on page 201 for additional information.

The Host Interface PDI is used to support HBI and SPI modes, as described in Section 14.0, "Chip Mode Configuration,"

on page 296.

The configuration of the enabled PDI is controlled via the PDI Configuration Register and Extended PDI Configuration

exists.

12.4

Digital I/O PDI

The Digital I/O PDI provides 16 configurable digital I/Os (DIGIO[15:0]) to be used for simple systems without a host

controller. The Digital I/O Output Data Register is used to control the output values, while the Digital I/O Input Data Reg-

ister is used to read the input values. Each 2-bit pair of the digital I/Os is configurable as an input or output. The direction

is selected by the Extended PDI Configuration Register, which is configured via EEPROM (Refer to Section 12.8,

"EEPROM Configurable Registers," on page 201 for additional information). The Digital I/Os can also be configured to

bi-directional mode, where the outputs are driven and latched externally and then released so that the input data can

be sampled. Bi-directional operation is selected via the Unidirectional/Bidirectional Mode bit of the PDI Configuration

12.4.1

OUTPUT WATCHDOG BEHAVIOR

The watchdog control of the digital outputs can be configured to specify if the expiration of the SyncManager Watchdog

will have an immediate effect on the I/O signals (output reset immediately after watchdog timeout) or if the effect is

delayed until the next output event (output reset with next output event). The choice is determined by the Watchdog

Behavior bit of the PDI Configuration Register. The PDI Configuration Register is initialized from the contents of

EEPROM. Refer to Section 12.8, "EEPROM Configurable Registers," on page 201 for additional information.

12.4.2

OE_EXT OUTPUT WATCHDOG BEHAVIOR

For external watchdog implementations, the WD_TRIG (watchdog trigger) pin can be used. A pulse is generated if the

SyncManager Watchdog is triggered. In this case, the internal SyncManager Watchdog should be disabled, and the

external watchdog may use the OE_EXT pin to reset the I/O signals if the watchdog is expired.

The OUTVALID Mode bit of the PDI Configuration Register controls if WD_TRIG is mapped onto the OUTVALID pin.

The PDI Configuration Register is initialized from the contents of EEPROM. Since there is a dedicated WD_TRIG pin,

this bit is normally set to 0 in the EEPROM.

12.4.3

INPUT DATA SAMPLING

Digital inputs can be configured to be sampled in four ways, at the start of each Ethernet frame, at the rising edge of the

LATCH_IN pin, at Distributed Clocks SYNC0 events or at Distributed Clocks SYNC1 events. The choice of sampling

mode is determined by the Input Data Sample Selection bits of the PDI Configuration Register. The PDI Configuration

12.4.4

OUTPUT DATA UPDATING

Digital outputs can be configured to be update four ways, at the end of each Ethernet frame, with Distributed Clocks

SYNC0 events, with Distributed Clocks SYNC1 events or at the end of an EtherCAT frame which triggered the Process

Data Watchdog. The choice of sampling mode is determined by the Output Data Sample Selection bits of the PDI Con-

figuration Register. The PDI Configuration Register is initialized from the contents of EEPROM.

12.4.5

OUTVALID POLARITY

The output polarity of the OUTVALID pin is determined by the OUTVALID Polarity bit of the PDI Configuration Register.

The PDI Configuration Register is initialized from the contents of EEPROM.

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