LAN9252SLASHML datasheet(197/329 Pages) MICROCHIP

197 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 197

LAN9252

12.2

Distributed Clocks

The device supports 64-bit distributed clocks as detailed in the following sub-sections.

12.2.1

SYNC/LATCH PIN MULTIPLEXING

The EtherCAT Core provides two input pins (LATCH0 and LATCH1) which are used for time stamping of external

events. Both rising edge and falling edge time stamps are recorded. These pins are shared with the SYNC0 and SYNC1

output pins, respectively, which are used to indicate the occurrence of time events. The functions of the SYNC0/LATCH0

and SYNC1/LATCH1 pins are determined by the SYNC0/LATCH0 Configuration and SYNC1/LATCH1 Configuration

bits of the Sync/Latch PDI Configuration Register, respectively.

When set for SYNC0/SYNC1 functionality, the output type (Push-Pull vs. Open Drain/Source) and output polarity are

determined by the SYNC0 Output Driver/Polarity and SYNC1 Output Driver/Polarity bits of the Sync/Latch PDI Config-

uration Register.

12.2.2

SYNC IRQ MAPPING

The SYNC0 and SYNC1 states can be mapped into the State of DC SYNC0 and State of DC SYNC1 bits of the AL Event

Request Register, respectively. The mapping of the SYNC0 and SYNC1 states is enabled by the SYNC0 Map and

SYNC1 Map bits of the Sync/Latch PDI Configuration Register, respectively.

12.2.3

SYNC PULSE LENGTH

The SYNC0 and SYNC1 pulse length is controlled via the Pulse Length of SyncSignals Register. The Pulse Length of

SyncSignals Register is initialized from the contents of EEPROM. Refer to Section 12.8, "EEPROM Configurable Reg-

isters," on page 201 for additional information.

12.2.4

SYNC/LATCH I/O TIMING REQUIREMENTS

This section specifies the SYNC0/LATCH0 and SYNC1/LATCH1 input and output timings.

Note:

The Sync/Latch PDI Configuration Register is initialized from the contents of EEPROM. Refer to Section

12.8, "EEPROM Configurable Registers," on page 201 for additional information.

Note:

The Sync/Latch PDI Configuration Register is initialized from the contents of EEPROM. Refer to Section

12.8, "EEPROM Configurable Registers," on page 201 for additional information.

FIGURE 12-1:

ETHERCAT SYNC/LATCH TIMING DIAGRAM

TABLE 12-1:

ETHERCAT SYNC/LATCH TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

tdc_latch

Time between LATCH0 or LATCH1 events

tdc_sync_jitter SYNC0 or SYNC1 output jitter

LATCH0/1

SYNC0/1

tdc_latch

tdc_sync_jitter

output event time

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