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Frequency (MHz)

010

40

30

20

50

45

40

35

30

25

20

G = +2V/V

OPA698

402

Ω

+2.5V

−2.5V

402

Ω

50

Ω

P

I

500

Ω

PO

G044

+VS

−VS

Output Voltage Swing (V

PP)

0.5

1.0

2.0

1.5

2.5

−65

−70

−75

−80

−85

−90

3rd−Harmonic

2nd−Harmonic

G043

RL = 500 Ω to VS/2

f = 5 MHz

VH = VCPP/2 + VCM + 0.5 V

VL = VCPP/2 + VCM + 0.5 V

Limiter Headroom (V)

0

0.5

2

1.5

1

2.5

100

75

50

25

0

−25

−50

−75

−100

Maximum Over Temperature

G046

Limiter Headroom = +VS − VH

= VL − (−VS)

Current = IVH or − IVL

Minimum

Over Temperature

Limit Voltages - 2.5V

0.9

1.0

1.1

1.6

1.7

1.4

1.5

1.2

1.3

1.8

-40

-45

-50

-55

-60

-65

-70

-75

-80

V

O = VCM ±1VP

f = 5MHz

R

L = 500Ω

3rd-Harmonic

2nd-Harmonic

G045

TYPICAL APPLICATIONS

Wideband Voltage Limiting Operation

OPA698M

SGLS287A – MAY 2005 – REVISED MARCH 2006

TYPICAL CHARACTERISTICS — V

S = +5 V (continued)

HARMONIC DISTORTION vs OUTPUT VOLTAGE

2-TONE, 3RD ORDER

INTERMODULATION INTERCEPT

Figure 43.

Figure 44.

HARMONIC DISTORTION NEAR LIMITING VOLTAGES

LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE

Figure 45.

Figure 46.

The OPA698 is a voltage feedback amplifier that combines features of a wideband, high slew rate amplifier with

output voltage limiters. Its output can swing up to 1 V from each rail and can deliver up to 120 mA. These

capabilities make it an ideal interface to drive ADC, while adding overdrive protection for the ADC inputs.

Figure 47 shows the dc-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the ±5-V

Electrical Characteristics and Typical Characteristics. For test purposes, the input impedance is set to 50

Ω with

a resistor to ground and the output impedance is set to 500

Ω. Voltage swings reported in the specifications are

taken directly at the input and output pins. For the circuit of Figure 47, the total output load is 500

Ω || 804 Ω =

308

Ω. The voltage limiting pins are set to ±2 V through a voltage divider network between the +V

S and ground

for VH and between –VS and ground for VL. These limiter voltages are adequately bypassed with a 0.1-µF

ceramic capacitor to ground. The limiter voltages (VH and VL) and the respective bias currents (IVH and IVL) have

the polarities shown. One additional component is included in Figure 47. An additional resistor (174

Ω) is

included in series with the noninverting input. Combined with the 25-

Ω dc-source resistance looking back towards

the signal generator, this gives an input bias current-cancelling resistance that matches the 200-

Ω source

resistance seen at the inverting input (see the dc accuracy and offset control section). The power-supply bypass

13

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