PCF85063TP datasheet(30/52 Pages) NXP

30 / 52 page

PCF85063TP

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Product data sheet

Rev. 4 — 6 May 2015

30 of 52

NXP Semiconductors

PCF85063TP

Tiny Real-Time Clock/calendar

[1]

For reliable oscillator start-up at power-on: VDD(po)min =VDD(min) +0.3 V.

[2]

Timer source clock = 1⁄60 Hz, level of pins SCL and SDA is VDD or VSS.

[3]

Tested on sample basis.

[4]

The I2C-bus interface of PCF85063TP is 5 V tolerant.

[5]

Implicit by design.

[6]

Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series:

Oscillator

f

osc/fosc

relative oscillator frequency

variation

V

DD =200 mV;

Tamb =25 C

0.075

ppm

CL(itg)

integrated load capacitance

on pins OSCO, OSCI

[6]

CL = 7 pF

4.2

9.8

CL = 12.5 pF

7.5

12.5

17.5

series resistance

100



Table 31.

Static characteristics …continued

VDD = 0.9 V to 5.5 V; VSS =0V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs =60 k; CL = 7 pF; unless otherwise

specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Litg



OSCI

OSCO





OSCI

OSCO



--------------------------------------------

Tamb =25 C; CLKOUT disabled.

(1) VDD =5.0 V.

(2) VDD =3.3 V.

Fig 20. Typical IDD with respect to fSCL

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