LP38842

SNVS291C – DECEMBER 2004 – REVISED APRIL 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

CONNECTION DIAGRAM

Figure 1. TO-220, Top View

Figure 2. DDPAK/TO-263, Top View

Pin DESCRIPTIONS

Pin Name

Description

BIAS

The bias pin is used to provide the low current bias voltage to the chip which operates the internal circuitry and

provides drive voltage for the N-FET.

OUTPUT

The regulated output voltage is connected to this pin.

GND

This is both the power and analog ground for the IC. Note that both pin three and the tab of the TO-220 and

DDPAK/TO-263 packages are at ground potential. Pin three and the tab should be tied together using the PC board

copper trace material and connected to circuit ground.

INPUT

The high current input voltage which is regulated down to the nominal output voltage must be connected to this pin.

Because the bias voltage to operate the chip is provided separately, the input voltage can be as low as a few hundred

millivolts above the output voltage.

SHUTDOWN

This provides a low power shutdown function which turns the regulated output OFF. Tie to VBIAS if this function is not

used.

BLOCK DIAGRAM

2

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