VDD

RESET

Reset Delay (tD) = 5.8 ms

VDD

RESET

Reset Delay (tD)= 654 ms

13

LP3470A

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9.2.3 Application Curves

Two capacitor values for CSRT (0.01 µF and 1 µF) are used as examples to show the programmability of the

output time delay as shown in Figure 12 and Figure 13.

Figure 12. Reset Delay Time with 0.01-µF Capacitor at SRT

Figure 13. Reset Delay Time with 1-µF Capacitor at SRT