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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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68HC05PL4B датащи(PDF) 69 Page - Freescale Semiconductor, Inc |
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68HC05PL4B датащи(HTML) 69 Page - Freescale Semiconductor, Inc |
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69 / 98 page  April 30, 1998 GENERAL RELEASE SPECIFICATION MC68HC05PL4 INSTRUCTION SET REV 2.0 12-1 SECTION 12 INSTRUCTION SET This section describes the addressing modes and instruction types. 12.1 ADDRESSING MODES The CPU uses eight addressing modes for exibility in accessing data. The addressing modes de ne the manner in which the CPU nds the data required to execute an instruction. The eight addressing modes are the following: • Inherent • Immediate • Direct • Extended • Indexed, No Offset • Indexed, 8-Bit Offset • Indexed, 16-Bit Offset • Relative 12.1.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry ag (SEC) and increment accumulator (INCA). Inherent instructions require no memory address and are one byte long. 12.1.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no memory address and are two bytes long. The opcode is the rst b yte, and the immediate data value is the second byte. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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