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INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

TRUTH TABLE

X : Don’t Care

Z : High Impedance

LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays

PIN No

SYMBOL

NAME AND FUNCTION

1OE

3-State Output Enable

(Active LOW)

2, 5, 6, 9, 12,

15, 16,19

Q0 to Q7

3-State Outputs

3, 4, 7, 8, 13,

14, 17, 18

D0 to D7

Data Inputs

11

CLOCK

Clock Input (LOW-to-HIGH

Edge Trigger)

10

GND

Ground (0V)

20

Positive Supply Voltage

INPUTS

OUTPUT

OE

CK

D

Q

H

XXZ

L

X

NO CHANGE

LL

L

LH

H