M29W800AB datasheet(6/40 Pages) STMICROELECTRONICS

6 / 40 page

M29W800AT, M29W800AB

6/40

Command Interface

Instructions, made up of commands written in cy-

cles, can be given to the Program/Erase Controller

through a Command Interface (C.I.). For added

data protection, program or erase execution starts

after 4 or 6 cycles. The first, second, fourth and

fifth cycles are used to input Coded cycles to the

C.I. This Coded sequence is the same for all Pro-

gram/Erase Controller instructions. The 'Com-

mand' itself and its confirmation, when applicable,

are given on the third, fourth or sixth cycles. Any

incorrect command or any improper command se-

quence will reset the device to Read Array mode.

Instructions

Seven instructions are defined to perform Read

Array, Auto Select (to read the Electronic Signa-

ture or Block Protection Status), Program, Block

Erase, Chip Erase, Erase Suspend and Erase Re-

sume.

The internal P/E.C. automatically handles all tim-

ing and verification of the Program and Erase op-

erations. The

Status Register Data Polling,

Toggle, Error bits and the RB output may be read

at any time, during programming or erase, to mon-

itor the progress of the operation.

Instructions are composed of up to six cycles. The

first two cycles input a Coded sequence to the

Command Interface which is common to all in-

structions (see Table 8).

The third cycle inputs the instruction set-up com-

mand. Subsequent cycles output the addressed

data, Electronic Signature or Block Protection Sta-

tus for Read operations. In order to give additional

data protection, the instructions for Program and

Block or Chip Erase require further command in-

puts. For a Program instruction, the fourth com-

mand cycle inputs the address and data to be

programmed. For an Erase instruction (Block or

Chip), the fourth and fifth cycles input a further

Coded sequence before the Erase confirm com-

mand on the sixth cycle. Erasure of a memory

block may be suspended, in order to read data

from another block or to program data in another

block, and then resumed. When power is first ap-

plied or if VCC falls below VLKO, the command in-

terface is reset to Read Array.

Figure 3. TSOP Connections

Figure 4. SO Connections

DQ3

DQ9

DQ2

DQ0

DQ6

DQ13

A17

A10

DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

AI02179

M29W800T

M29W800B

DQ8

A18

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14

VSS

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A–1

DQ5

DQ2

DQ3

VCC

DQ11

DQ4

DQ14

AI02181

M29W800T

M29W800B

DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10

DQ12

A17

A18

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