LM4921

SNAS178E – JULY 2003 – REVISED MAY 2013

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APPLICATION INFORMATION

SPI OPERATIONAL DESCRIPTION

The serial data bits are organized into a field which contains 16 bits of data defined by Table 1. Bits 1 & 2

determine the output mode of the LM4921 as shown in Table 2. Bits 7 through 11 determine the volume level

setting as illustrated by Table 3. Bit 12 sets the Bypass capacitor charging time.

Table 1. Bit Allocation

BIT #

Default Val

Function

Description

0 (LSB)

0

RESET_B

RESET_B = 0, Resets the DAC

Must be high for the part to run.

1

0

MODE CONTROL

See Table 2

2

0

3

0

MASTER/SLAVE

0 = SLAVE, 1 = MASTER

4

0

RESOLUTION

0 = 16 bit, 1 = 32 bit

5

0

RESERVED

Should always be set to '1'

6

0

ZERO CROSSING SET

0 = ZXD ENABLE, 1 = ZXD DISABLE

7

0

VOLUME CONTROL

See Table 3

8

0

9

0

10

0

11

0

12

0

BYP CHARGE RATE

0 = 1X, 1 = 2X

13

0

RESERVED

14

0

RESERVED

15 (MSB)

0

RESERVED

Should always be set to '0'

MODE CONTROL

Sets the modes as outlined in Table 2.

Table 2. Output Mode Selection (Bits 1 & 2 above)

Output Mode #

BIT 2

BIT 1

MODE

0

0

0

SD

1

0

1

STANDBY

2

1

0

MUTE

3

1

1

ACTIVE

Shutdown turns off the part completely for maximum power savings. The Standby mode turns off the clock but

still consumes more power than the shutdown mode. However, coming out of standby mode allows the part to

turn back on faster than from shutdown. In Mute mode the clocks remain on which uses more power but allows

faster recovery and the ability to supply clock signals to other devices which is important when the part is used in

master mode. Active mode turns the part on for normal operation.

MASTER/SLAVE SELECT

Allows the part to act as a master and supply the clock for the rest of the system or be a slave to the system

clock.

RESOLUTION SET

Sets the resolution to be either 16 or 32 bits of stereo audio information. For most applications this will be set at

16 bits.

12

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