R/W

Bit 0

1

Bit 1

1

Bit 2

0

Bit 3

0

Bit 4

0

Bit 5

1

Bit 7

1

Bit 6

MSB

LSB

I

2

C Slave Address (chip address)

start

msb Chip Address lsb

w

ack

msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

ack from slave

ack from slave

ack from slave

SCL

SDA

start

Id = 63h

w

ack

addr = 0Ah

ack

ack

Data = 03h

stop

SDA

Start Condition

Stop Condition

SCL

S

P

LM3642

www.ti.com

SNVS891H – SEPTEMBER 2012 – REVISED SEPTEMBER 2015

Programming (continued)

Figure 13. Start and Stop Conditions

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each

byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the

master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM3642 pulls down

the SDA line during the 9th clock pulse, signifying an acknowledge. The LM3642 generates an acknowledge

after each byte is received. There is no acknowledge created after data is read from the LM3642.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). The LM3642 7-bit address is 0x63. For the eighth bit, a '0' indicates

a WRITE and a '1' indicates a READ. The second byte selects the register to which the data will be written. The

third byte contains data to write to the selected register.

w = write (SDA = "0")

r = read (SDA = "1")

ack = acknowledge (SDA pulled down by either master or slave)

id = chip address, 63h for LM3642

Figure 14. Write Cycle

7.5.1.4 I2C-Compatible Chip Address

The device address for the LM3642 is 1100011 (63). After the START condition, the I2C-compatible master

sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE, and R/W = 1

indicates a READ. The second byte following the device address selects the register address to which the data

will be written. The third byte contains the data for the selected register.

Figure 15. I2C-Compatible Device Address

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