LM3537

SNVS634B – JUNE 2011 – REVISED MAY 2013

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LOGIC INTERFACE CHARACTERISTICS

(1) (2)

Symbol

Parameter

Condition

Min

Typ

Max

Units

I2C-Compatible Interface Timing Specifications (SCL, SDA)(3)

t1

SCL (Clock Period)

See(4)

2.5

µs

t2

Data In Setup Time to SCL High

100

ns

t3

Data Out stable After SCL Low

0

ns

SDA Low Setup Time to SCL Low

t4

100

ns

(Start)

SDA High Hold Time After SCL High

t5

100

ns

(Stop)

I2C-Compatible Interface Voltage Specifications (SCL, SDA)

VIL

Input Logic Low "0"

2.7V

≤ VIN_A ≤ 5.5V

0

0.45

V

VIH

Input Logic High "1"

2.7V

≤ VIN_A ≤ 5.5V

1.25

VIN_A

V

VOL

Output Logic Low "0"

ILOAD = 3mA

400

mV

Logic inputs HWEN and PWM

Reset

0

0.45

VHWEN

HWEN Voltage Thresholds

2.7V

≤ VIN_A ≤ 5.5V

V

Normal Operation

1.2

VIN_A

LEDs Off

0

0.45

VPWM

PWM Voltage Thresholds

2.7V

≤ VIN_A ≤ 5.5V

V

LEDs On

1.2

VIN_A

ALS interrupt

VOL-INT

Interrupt Output Logic Low '0'

ILOAD = 3mA

400

mV

Logic outputs GPO1, GPO2(5)

VOL

Output Low Level

IOUT = 3 mA

0.3

0.5

V

VOUT_S

VOUT_S

VOH

Output High Level

IOUT = −2 mA

V

−0.5

–0.3

(1)

All voltages are with respect to the potential at the GND pins.

(2)

Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most

likely norm.

(3)

SCL and SDA should be glitch-free in order for proper device control to be realized. See Figure 2 for timing specification details.

(4)

SCL is tested with a 50% duty-cycle clock.

(5)

VOUT_S = SBIAS pin output voltage. The voltage level of the GPOs depends on the sbias_en-bit: '1'; GPOs will behave as push-pull

outputs and will reference the high-side to the voltage of SBIAS. '0'; GPOs will act as open-drain outputs (default). In the open-drain

configuration, they can be high-side referenced to any voltage equal to, or less than, the VIN_A of the LM3537. Output High Level (VOH)

specification is valid only for push-pull -type outputs.

6

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