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INA159-EP датащи(PDF) 3 Page - Texas Instruments |
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INA159-EP датащи(HTML) 3 Page - Texas Instruments |
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3 / 19 page ![]() INA159 SBOS333B − JULY 2005 − REVISED OCTOBER 2005 www.ti.com 3 ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits apply over the specified temperature range, TA = −40°C to +125°C. At TA = +25°C, RL = 10kΩ connected to VS/2, REF pin 1 connected to ground, and REF pin 2 connected to VREF = 5V, unless otherwise noted. INA159 PARAMETER CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE(1) RTO Initial (1) VOS VS = ±2.5V, Reference and Input Pins Grounded ±100 ±500 µV vs Temperature ±1.5 µV/°C vs Power Supply PSRR VS = ±0.9V to ±2.75V ±20 ±100 µV/V Reference Divider Accuracy(2) ±0.002 ±0.024 % over Temperature ±0.002 % INPUT IMPEDANCE(3) Differential 240 kΩ Common-Mode 60 kΩ INPUT VOLTAGE RANGE RTI Common-Mode Voltage Range VCM Positive 17.5 V Negative −12.5 V Common-Mode Rejection Ratio CMRR VCM = −10V to +10V, RS = 0Ω 80 96 dB over Temperature 94 dB OUTPUT VOLTAGE NOISE(4) RTO f = 0.1Hz to 10Hz 10 µVPP f = 10kHz 30 nV/√Hz GAIN VREF2 = 4.096V, RL Connected to GND, (VIN+) − (VIN−) = −10V to +10V, VCM = 0V Initial G 0.2 V/V Error ±0.005 ±0.024 % vs Temperature ±1 ppm/°C Nonlinearity ±0.0002 % of FS OUTPUT Voltage, Positive VREF2 = 4.096V, RL Connected to GND (V+) − 0.1 (V+) − 0.02 V Voltage, Negative VREF2 = 4.096V, RL Connected to GND (V−) + 0.048 (V−) + 0.01 V Current Limit, Continuous to Common ±60 mA Capacitive Load See Typical Characteristic pF Open-Loop Output Impedance RO f = 1MHz, IO = 0 110 Ω FREQUENCY RESPONSE Small-Signal Bandwidth −3dB 1.5 MHz Slew Rate SR 15 V/µs Settling Time, 0.01% tS 4V Output Step, CL = 100pF 1 µs Overload Recovery Time 50% Overdrive 250 ns POWER SUPPLY Specified Voltage Range VS +5 V Operating Voltage Range +1.8 +5.5 V Quiescent Current IQ IO = 0mA, VS = ±2.5V, Reference and Input Pins Grounded 1.1 1.5 mA TEMPERATURE RANGE Specified Range −40 +125 °C Operating Range −40 +150 °C Storage Range −65 +150 °C Thermal Resistance qJA MSOP-8 Surface-Mount 150 °C/W (1) Includes effects of amplifier input bias and offset currents. (2) Reference divider accuracy specifies the match between the reference divider resistors using the configuration in Figure 2. (3) Internal resistors are ratio matched but have ±20% absolute value. (4) Includes effects of amplifier input current noise and thermal noise contribution of resistor network. |
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