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TS4268CS50 датащи(PDF) 5 Page - Taiwan Semiconductor Company, Ltd |
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TS4268CS50 датащи(HTML) 5 Page - Taiwan Semiconductor Company, Ltd |
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5 / 7 page ![]() Preliminary TS4268 180mA Ultra Low Dropout Voltage Regulator with Reset & Watchdog Function 5/7 Version: Preliminary Test Circuit Reset Timing The power-on reset delay time is defined by charging time of an external capacitor CD which can be calculated as follow: CD = ( ∆trd x ID,C ) / ∆V Definitions: CD = delay capacitor ∆trd = delay time ID,C = charge current, typical 12uA ∆V = VDU, typical 1.8 V VDU = upper delay switching threshold at CD for reset delay time The reset reaction time trr is the time it takes the voltage regulator to set the reset out LOW after the output voltage has dropped below the reset threshold. It is typically 1uS for delay capacitor of 47nF. For other values for CD the reaction time can be estimated using the following equation: Trr ≈ 20 s/F x CD |
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