M25PE16-VMP6TP datasheet(14/56 Pages) STMICROELECTRONICS

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Operating features

M25PE16

14/56

4.7

Status Register

The Status Register contains a number of status and control bits that can be read or set (as

appropriate) by using specific instructions. See Section 6.4: Read Status Register (RDSR)

for a detailed description of the Status Register bits.

4.8

Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI

device can operate correctly in the presence of excessive noise. To help combat this and to

meet the needs of modularized applications, the M25PE16 features the following flexible

data protection mechanisms:

4.8.1

Protocol-related protections

●

Power On Reset and an internal timer (tPUW) can provide protection against inadvertent

changes while the power supply is outside the operating specification.

●

Program, Erase and Write instructions are checked that they consist of a number of

clock pulses that is a multiple of eight, before they are accepted for execution.

●

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

–Power-up

–

Reset (RESET) driven Low

–

Write Disable (WRDI) instruction completion

–

Page Write (PW) instruction completion

–

Write Status Register (WRSR) instruction completion

–

Page Program (PP) instruction completion

–

Write to Lock Register (WRLR) instruction completion

–

Page Erase (PE) instruction completion

–

SubSector Erase (SSE) instruction completion

–

Sector Erase (SE) instruction completion

–

Bulk Erase (BE) instruction completion

●

The Reset (RESET) signal can be driven Low to freeze and reset the internal logic. For

the specific cases of Program and Write cycles, the designer should refer to

Section 6.5: Write Status Register (WRSR), Section 6.9: Page Write (PW),

Section 6.10: Page Program (PP), Section 6.12: Page Erase (PE), Section 6.13: Sector

Erase (SE) and Section 6.14: SubSector Erase (SSE), and to Table 12: Device status

after a RESET Low pulse.

●

In addition to the low power consumption feature, the Deep Power-down mode offers

extra software protection from inadvertent Write, Program and Erase instructions while

the device is not in active use.

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