74ACT11238

3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

SCAS054 – NOVEMBER 1988 – REVISED APRIL 1993

POST OFFICE BOX 655303

2–2

DMUX

0

2

G

0

7

A

B

C

G1

G2A

Y0

Y1

Y2

Y3

Y5

Y6

Y7

G2B

15

14

13

11

10

9

16

1

2

3

6

7

8

BIN/OCT

1

2

A

B

C

G1

G2A

Y0

Y1

Y2

Y3

Y5

Y6

Y7

G2B

15

14

13

11

10

9

16

1

2

3

6

7

8

4

0

1

2

3

0

1

2

3

Y4

5

4

Y4

5

4

5

6

7

&

EN

&

5

6

7

† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

Y0

A

15

16

Y1

1

Y2

2

Y3

3

Y4

5

Y5

6

Y6

7

Y7

8

B

14

C

13

G1

11

G2A

10

G2B

9