EN

PHY2

DAC2

200 MHz

Clock

Generation

100 MHz

CDCLVD 2102

ADC2

CDCLVD2102

www.ti.com

SCAS904A – MAY 2010 – REVISED JUNE 2010

Dual 1:2 Low Additive Jitter LVDS Buffer

Check for Samples: CDCLVD2102

1

FEATURES

DESCRIPTION

•

Dual 1:2 Differential Buffer

•

Low Additive Jitter <300 fs RMS in 10-kHz to

The CDCLVD2102 clock buffer distributes two clock

inputs (IN0, IN1) to a total of 4 pairs of differential

20-MHz

LVDS clock outputs (OUT0, OUT3). Each buffer block

•

Low Within Bank Output Skew of 15 ps (Max)

consists of one input and 2 LVDS outputs. The inputs

•

Universal Inputs Accept LVDS, LVPECL,

can either be LVDS, LVPECL, or LVCMOS.

LVCMOS

The CDCLVD2102 is specifically designed for driving

•

One Input Dedicated for Two Outputs

50-

Ω transmission lines. If driving the inputs in single

•

Total of 4 LVDS Outputs, ANSI EIA/TIA-644A

ended mode, the appropriate bias voltage (VAC_REF)

Standard Compatible

should be applied to the unused negative input pin.

•

Clock Frequency up to 800 MHz

Using the control pin (EN), outputs can be either

disabled or enabled. If the EN pin is left open two

•

2.375–2.625V Device Power Supply

buffers with all outputs are enabled, if switched to a

•

LVDS Reference Voltage, VAC_REF, Available for

logical "0" both buffers with all outputs are disabled

Capacitive Coupled Inputs

(static logical "0"), if switched to a logical "1", one

•

Industrial Temperature Range –40°C to 85°C

buffer with two outputs is disabled and another buffer

with two outputs is enabled. The part supports a fail

•

Packaged in 3mm × 3mm 16-Pin QFN (RGT)

safe function. It incorporates an input hysteresis,

•

ESD Protection Exceeds 3 kV HBM, 1 kV CDM

which prevents random oscillation of the outputs in

absence of an input signal.

APPLICATIONS

The device operates in 2.5V supply environment and

•

Telecommunications/Networking

is characterized from –40°C to 85°C (ambient

•

Medical Imaging

temperature). The CDCLVD2102 is packaged in

•

Test and Measurement Equipment

small 16-pin, 3-mm × 3-mm QFN package.

•

Wireless Communications

•

General Purpose Clocking

Figure 1. Application Example

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2010, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.