CD74FCT273

BiCMOS OCTAL D-TYPE FLIP-FLOP

WITH RESET

SCBS737A – JULY 2000 – REVISED JULY 2000

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D BiCMOS Technology With Low Quiescent

Power

D Buffered Inputs

D Direct Clear Input

D 48-mA Output Sink Current

D Output Voltage Swing Limited to 3.7 V

D Controlled Output Edge Rates

D Input/Output Isolation From VCC

D SCR Latch-Up-Resistant BiCMOS Process

and Circuit Design

D Applications Include:

– Buffer/Storage Registers

– Shift Registers

– Pattern Generators

D Package Options Include Plastic

Small-Outline (M) Package and Standard

Plastic (E) DIP

description

The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR) input. This device uses

a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that

limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V)

reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and

ground bounce and their effects during simultaneous output switching. The output configuration also enhances

switching speed and is capable of sinking 48 mA.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not

directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the

D input has no effect at the output. All eight flip-flops are controlled by a common clock (CLK) and a common

reset (CLR). The outputs are placed in a low state when CLR is taken low, independent of the CLK.

The CD74FCT273 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLR

CLK

D

OUTPUT

Q

L

X

X

L

H

↑

HH

H

↑

LL

H

L

X

Q0

Copyright

© 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

E OR M PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

CLR

1Q

1D

2D

2Q

3Q

3D

4D

4Q

GND

VCC

8Q

8D

7D

7Q

6Q

6D

5D

5Q

CLK