General Note

TT Electronics reserves the right to make changes in product specification without

notice or liability. All information is subject to TT Electronics’ own data and is

considered accurate at time of going to print.

TT Electronics | OPTEK Technology

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Rev C, 4/27/2023

Page 7

© TT electronics plc

FlexSense® I-Series Programmable

Incremental Encoder

FS210/FS310 Datasheet

Characteristic

Symbol Conditions

Min

Typ

Max

Unit Notes

Input high voltage

VIH:M

0.7*VDD

V

Input leakage current

IL:M

0V ≤ V(pin) ≤ VDD, at 25°C

-0.1

0.1

µA

PREVENTIVE MAINENANCE OUTPUT CHARACTERISTICS

Proportional-to-absolute-

temperature output current

IPTAT

Tj = 25°C

10.4

µA

Tj = 125°C

14.8

µA

Wobble-detect coefficient

kW

4

µA/V2

I2C PIN CHARACTERISTICS

Input low voltage

VIL

0.3*VDD

V

Input high voltage

VIH

0.7*VDD

V

Output low current

IOL

VOL = 0.4V

3

mA

Output fall time

tOF

From VIH(min) to VIL(max)

250

ns

Input capacitance

CI

Presented by the device only

10

pF

I2C MASTER/SYSTEM REQUIREMENTS

SCL low time

tLOW

1.3

µs

SCL high time

tHIGH

0.6

µs

START-condition setup time

tSU;STA

VSCL↑ → VSDA↓

0.6

µs

START-condition hold time

tHD;STA

VSDA↓ → VSCL↓

0.6

µs

Data setup time

tSU;DAT

VSDA↕ → VSCL↑; for bits being written from

the master to this device

100

µs

Data hold time

tHD;DAT

VSCL↓ → VSDA↕; for bits being written from

the master to this device

0

µs

Data valid wait time

tVD;DAT

VSCL↓ → VSDA valid; for bits being read from

this device by the master

0.9

µs

STOP-condition setup time

tSU;STO

VSCL↑ → VSDA↑

0.6

µs

Bus free time (between STOP and

next START)

tBUF

VSDA↑ → VSDA↓

1.3

µs

Total capacitance, each of SCL and

SDA

CB

Sum of on-chip (CI) and off-chip

capacitances

400

pF

1

Thermal self-heating must not increase junction temperature beyond 135°C in normal operation.

2

Tj > TjSL causes output drivers to be disabled, most on-chip static current consumption (LED driver, TIAs, interpolator)

to be turned off, and the interrupt status bit INTR<4> to be set to 'b1. Additionally, it causes the IRQZ pin level to be

driven to 'b0 if the interrupt mask bit INTR<0> is 'b1. Once the shutdown threshold is tripped, the part remains in

shutdown until the user executes an I2C read access to the INTR register or until a power-on reset event occurs.