General Note

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notice or liability. All information is subject to TT Electronics’ own data and is

considered accurate at time of going to print.

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Rev C, 4/27/2023

Page 28

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FlexSense® I-Series Programmable

Incremental Encoder

FS210/FS310 Datasheet

Table 27. LEDLV field description

Bits

Description

ILKR

Actual LEDK drive current; 0.6mA/LSB nominally; equal to ILK if C_OZ = 0

C_OZR

Read-only duplicate of C_OZ bit in ILED register

Alarm Control

• Four types of events cause the FS210/FS310 to register an alarm condition when detected:

o

Power-up sequence initiated. (Alarm condition ends when power-up sequence is complete.)

o

Control loop out of regulation for closed-loop LED-drive control. (Alarm condition ends when control loop re-

enters regulation.)

o

On-chip junction temperature exceeds a user-configurable alarm trip point. (Alarm condition ends when

junction temperature falls below thermal-alarm trip point.)

o

On-chip junction temperature exceeds approximately 165°C, at which point the device might suffer damage.

(Power-cycling required to terminate alarm condition, even if junction temperature falls below 165°C.)

• The presence of an alarm condition causes the corresponding status bit in the INTR register to be set to 1. The

status bit is cleared to 0 only upon an I2C read access to INTR or upon a power-on reset. The disappearance of the

alarm condition alone, without such an I2C read access or POR event, is insufficient to clear an interrupt status bit to

0. Additionally, the presence of a (Tj > 165°C) alarm condition, because it suggests excessive power dissipation,

causes all current-consuming circuitry in the device to be shut off. Accordingly, this alarm condition is termed a

thermal-shutdown alarm condition.

• Unmasked alarm conditions cause the device’s open-drain IRQZ pin to be driven low; masked alarm conditions

cause no activity on the IRQZ pin. Power-on-sequence alarm conditions are unmaskable and therefore always

cause IRQZ to be driven low. The other three alarm conditions are masked (and therefore cause no IRQZ activity) if

the corresponding mask bit in the INTR register is cleared to 0 and unmasked (and therefore do cause IRQZ activity)

if the corresponding mask bit in INTR is set to 1. IRQZ is driven low only for as long as an unmasked alarm condition

persists: the termination of an unmasked alarm condition causes the device to release the IRQZ pin, even though

the corresponding INTR status bit stays set to 1 until an I2C read access or POR event.

Thermal Alarm Register (TALM: [0x0888])

Table 28. TALM register definition.

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

TTRM

TASET

Table 29. TALM field description.

Bits

Description

TASET

Thermal alarm trip point encoding: Trip point (TjAL) = 200°C – 9°/LSB

TTRM

Thermal accuracy trim (An I2C write access to TALM to change TASET should be preceded by an I2C

read access to ascertain the state of TTRM so that the I2C write access does not change TTRM.)