ADS7844 datasheet(13/24 Pages) TI2

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ADS7844

SBAS100A

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Data Format

The ADS7844 output data is in straight binary format as

shown in Figure 7. This figure shows the ideal output code

for the given input voltage and does not include the effects

of offset, gain, or noise.

FS = Full-Scale Voltage = V

REF

1 LSB = V

REF/4096

FS – 1 LSB

11...111

11...110

11...101

00...010

00...001

00...000

1 LSB

Note 1: Voltage at converter input, after

multiplexer: +IN–(–IN). See Figure 2.

Input Voltage(1) (V)

FIGURE 7. Ideal Input Voltages and Output Codes.

POWER DISSIPATION

There are three power modes for the ADS7844: full power

(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),

and shutdown (SHDN LOW). The affects of these modes

varies depending on how the ADS7844 is being operated. For

example, at full conversion rate and 16 clocks per conver-

sion, there is very little difference between full power mode

and auto power-down. Likewise, if the device has entered

auto power-down, a shutdown (SHDN LOW) will not lower

power dissipation.

When operating at full-speed and 16-clocks per conversion

(as shown in Figure 4), the ADS7844 spends most of its time

acquiring or converting. There is little time for auto power-

down, assuming that this mode is active. Thus, the differ-

ence between full power mode and auto power-down is

negligible. If the conversion rate is decreased by simply

slowing the frequency of the DCLK input, the two modes

remain approximately equal. However, if the DCLK fre-

quency is kept at the maximum rate during a conversion, but

conversion are simply done less often, then the difference

between the two modes is dramatic. Figure 8 shows the

difference between reducing the DCLK frequency (“scal-

ing” DCLK to match the conversion rate) or maintaining

DCLK at the highest frequency and reducing the number of

conversion per second. In the later case, the converter

spends an increasing percentage of its time in power-down

mode (assuming the auto power-down mode is active).

If DCLK is active and CS is LOW while the ADS7844 is in

auto power-down mode, the device will continue to dissipate

some power in the digital logic. The power can be reduced

to a minimum by keeping CS HIGH. The differences in

supply current for these two cases are shown in Figure 9.

FIGURE 8. Supply Current vs Directly Scaling the Fre-

quency of DCLK with Sample Rate or Keeping

DCLK at the Maximum Possible Frequency.

10k

100k

SAMPLE (Hz)

100

1000

CLK = 2MHz

CLK = 16 • fSAMPLE

A = 25°C

CC = +2.7V

REF = +2.5V

PD1 = PD0 = 0

FIGURE 9. Supply Current vs State of CS.

10k

100k

SAMPLE (Hz)

0.00

0.09

CS LOW

(GND)

CS HIGH (+V

CC)

A = 25°C

CC = +2.7V

REF = +2.5V

CLK = 16 • fSAMPLE

PD1 = PD0 = 0

Operating the ADS7844 in auto power-down mode will

result in the lowest power dissipation, and there is no

conversion time “penalty” on power-up. The very first

conversion will be valid. SHDN can be used to force an

immediate power-down.

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS7844 circuitry. This is particu-

larly true if the reference voltage is low and/or the conver-

sion rate is high.

The basic SAR architecture is sensitive to glitches or sudden

changes on the power supply, reference, ground connec-

tions, and digital inputs that occur just prior to latching the

output of the analog comparator. Thus, during any single

conversion for an n-bit SAR converter, there are n “win-

dows” in which large external transient voltages can easily

affect the conversion result. Such glitches might originate

from switching power supplies, nearby digital logic, and

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