ADS1271

SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007

www.ti.com

7

TIMING CHARACTERISTICS: FRAME-SYNC FORMAT

SCLK

FSYNC

DOUT

DIN

t

DOHD

t

FPW

t

S

t

SF

t

SPW

t

SPW

t

FRAME

t

FPW

t

FS

t

DIHD

t

DDO

t

DIST

Bit 23 (MSB)

Bit 22

Bit 21

t

DOPD

CLK

t

CPW

t

CPW

t

CF

t

CLK

TIMING REQUIREMENTS: FRAME-SYNC FORMAT

for TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

tCLK

CLK period (1/fCLK)

37

10,000

ns

tCPW

CLK positive or negative pulse width

15

ns

tCF

Falling edge of CLK to falling edge of SCLK

−0.35 tCLK

0.35 tCLK

ns

High-Speed mode

256

CLK periods

tFRAME

Frame period (1/fDATA)

High-Resolution mode

256 or 512(1)

CLK periods

tFRAME

Frame period (1/fDATA)

Low-Power mode

256 or 512(1)

CLK periods

tFPW

FSYNC positive or negative pulse width

1

SCLK periods

tFS

Rising edge of FSYNC to rising edge of SCLK

5

ns

tSF

Rising edge of SCLK to rising edge of FSYNC

5

ns

SCLK period (SCLK must

High-Speed mode

τFRAME/64

τFRAME periods

tS

SCLK period (SCLK must

be continuously running)

High-Resolution mode

τFRAME/128

τFRAME periods

tS

be continuously running)

Low-Power mode

τFRAME/64

τFRAME periods

tSPW

SCLK positive or negative pulse width

0.4tSCLK

0.6tSCLK

ns

tDOHD(2)(3) SCLK falling edge to old DOUT invalid (hold time)

5

ns

tDOPD(2)

SCLK falling edge to new DOUT valid (propagation delay)

12

ns

tDDO(2)

Valid DOUT to rising edge of FSYNC

0

ns

tDIST

New DIN valid to falling edge of SCLK (setup time)

6

ns

tDIHD(3)

Old DIN valid to falling edge of SCLK (hold time)

6

ns

(1) The ADS1271 automatically detects either frame period (only 256 or 512 allowed).

(2) Load on DOUT = 20pF.

(3) tDOHD (DOUT hold time) and tDIHD (DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient

temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.