0.0001

0.001

0.01

0.1

1

10

0.1

1

3

Output Voltage (V)

100 Hz

1 kHz

10 kHz

Active Filter

Gain = 2V/V

RL = 10 kΩ

0.0001

0.001

0.01

0.1

1

10

0.1

1

3

Output Voltage (V)

100 Hz

1 kHz

10 kHz

Active Filter

Gain = 2V/V

RL = 600Ω

13

DRV632

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SLOS681C – JANUARY 2011 – REVISED AUGUST 2019

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Copyright © 2011–2019, Texas Instruments Incorporated

Typical Application (continued)

10.2.1 Design Requirements

In this design example, use the parameters listed in Table 2.

Table 2. Design Parameters

KEY PARAMETERS

VALUE

Supply Voltage

3.3 V

Supply Current

0.10 A

Load Impedance

600 Ω (minimum)

10.2.2 Detailed Design Procedure

10.2.2.1 Charge-Pump Flying, PVSS and Decoupling Capacitors

To transfer charge during the generation of the negative supply voltage, an 1-µF low equivalent-series-resistance

(ESR) charge-pump flying capacitor is used for this design. Similar 1-µF capacitors are placed in VSS, and as

close as possible to VDD. See Charge-Pump Flying Capacitor and PVSS Capacitor and Decoupling Capacitors

for details.

10.2.2.2 Second-Order Active Low-Pass Filters

With the help of the TI WEBENCH Filter Designer (www.ti.com/filterdesigner), the values of R1 = 15 kΩ, R2 = 30

kΩ, R3 = 43 kΩ, C1 = 47 pF, and C2 = 180 pF are proposed to design a second-order low-pass filter with a

differential-input and a single-ended output. See Using the DRV632 as a Second-Order Filter for details.

10.2.2.3 UVP Resistor Divider

R11 and R12 are placed to design a resistor divider. The shutdown threshold at the UVP pin is 1.25 V. See

External Undervoltage Detection for details.

10.2.3 Application Curves

Figure 10. Total Harmonic Distortion and Noise vs Output

Voltage

Figure 11. Total Harmonic Distortion and Noise vs Output

Voltage