Functional Description (Continued)

MAIN STATUS REGISTER

TLF9981 – 12

The Main Status Register is always located at address 0

regardless of the register block selected

D0

This read only bit is a general interrupt status bit that is

taken directly from the interrupt pins The bit is a one when

an interrupt is pending on either the INTR pin or the MFO

pin (when configured as an interrupt) This is unlike D3

which can be set by an internal event but may not cause an

interrupt This bit is reset when the interrupt status bits in the

Main Status Register are cleared

D1 – D3

These three bits of the Main Status Register are the

main interrupt status bits Any bit may be a one when any of

the interrupts are pending Once an interrupt is asserted the

m

P will read this register to determine the cause These

interrupt status bits are not reset when read Except for D1

to reset an interrupt a one is written back to the correspond-

ing bit that is being tested D1 is reset whenever the PFAIL

pin e logic 1 This prevents loss of interrupt status when

reading the register in a polled mode D1 and D3 are set

regardless of whether these interrupts are masked or not by

bits D6 and D7 of Interrupt Control Registers 0 and 1

D4 D5 and D7

General purpose RAM bits

D6

Bit D6 controls the register block to be accessed (see

memory map)

PERIODIC FLAG REGISTER

TLF9981 – 13

The Periodic Flag Register has the same bit for bit corre-

spondence as Interrupt Control Register 0 except for D6

and D7 For normal operation (ie not a single supply appli-

cation) this register must be written to on initial power up or

after an oscillator fail event D0 – D5 are read only bits D6

and D7 are readwrite

D0 – D5

These bits are set by the real time rollover events

(Time Change e 1) The bits are reset when the register is

read and can be used as selective data change flags

D6

This bit performs a dual function When this bit is read a

one indicates that an oscillator failure has occurred and the

time information may have been lost Some of the ways an

oscillator failure might be caused are failure of the crystal

shorting OSC IN or OSC OUT to GND or VCC removal of

crystal removal of battery when in the battery backed mode

(when a ‘‘0’’ is written to D6) lowering the voltage at the

VBB pin to a value less than 22V when in the battery

backed mode Bit D6 is automatically set to 1 on initial pow-

er-up or an oscillator fail event The oscillator fail flag is

reset by writing a one to the clock startstop bit in the Real

Time Mode Register with the crystal oscillating

When D6 is written to it defines whether the TCP is being

used in battery backed (normal) or in a single supply mode

application When set to a one this bit configures the TCP

for single power supply applications This bit is automatically

set on initial power-up or an oscillator fail event When set

D6 disables the oscillator reference circuit The result is that

the oscillator is referenced to VCC When a zero is written to

D6 the oscillator reference is enabled thus the oscillator is

referenced to VBB This allows operation in standard battery

standby applications

At initial power on if the DP8573A is going to be pro-

grammed for battery backed mode the VBB pin should be

connected to a potential in the range of 22V to VCC b

04V

For single supply mode operation the VBB pin should be

connected to GND and the PFAIL pin connected to VCC

D7

Writing a one to this bit enables the test mode register

at location 1F (see Table III) This bit should be forced to

zero during initialization for normal operation If the test

mode has been entered clear the test mode register before

leaving test mode (See separate test mode application

note for further details)

TIME SAVE CONTROL REGISTER

TLF9981 – 14

D0 – D5

General purpose RAM bits

D6

Not Available appears as logic 0 when read

D7

Time Save Enable bit controls the loading of real-time-

clock data into the Time Save RAM When a one is written

to this bit the Time Save RAM will follow the corresponding

clock registers and when a zero is written to this bit the time

in the Time Save RAM is frozen This eliminates any syn-

chronization problems when reading the clock thus negat-

ing the need to check for a counter rollover during a read

cycle

This bit must be set to a one prior to power failing to enable

the Time Save feature When the power fails this bit is auto-

matically reset and the time is saved in the Time Save RAM

REAL TIME MODE REGISTER

TLF9981 – 15

11