DAC7731EB datasheet(14/23 Pages) TI2

14 / 23 page

DAC7731

SBAS249B

www.ti.com

REFERENCE

OUTPUT

PIN STRAPPING

VSJ(1)

CONFIGURATION CONFIGURATION ROFFSET

RFB1

RFB2

Internal

0V to +10V

to VREF to VOUT to VOUT

+5V

Reference

–10V to +10V

to VOUT +3.333V

–5V to +5V

to AGND to VOUT to VOUT +1.666V

External

0V to VREF

to VREF to VOUT to VOUT

VREF/2

Reference

–VREF to VREF

to VOUT

VREF/3

–VREF/2 to VREF/2 to AGND to VOUT to VOUT

VREF/6

NOTE: (1) Voltage measured at VSJ for a given configuration.

APPLICATIONS

GAIN AND OFFSET CALIBRATION

The architecture of the DAC7731 is designed in such a way

as to allow for easily configurable offset and gain calibration

using a minimum of external components. The DAC7731

has built-in feedback resistors and output amplifier summing

points brought out of the package in order to make the

absolute calibration possible. Figures 9 and 10 illustrate the

relationship of offset and gain adjustments for the DAC7731

in a unipolar configuration and in a bipolar configuration,

respectively.

at +10V – 1LSB for the 0V to +10V or

±10V output range and

+5V – 1LSB for the

±5V output range. Figure 11 shows the

generalized external offset and gain adjustment circuitry

using potentiometers.

FIGURE 9. Relationship of Offset and Gain Adjustments for

VOUT = 0V to +10V Output Configuration.

Digital Input

Input =

FFFF

Input =

0000

Gain Adjust

Rotates

the Line

1LSB

+ Full Scale

(+V

REF)

Zero Scale

(AGND)

Offset Adjust Translates the Line

FIGURE 10. Relationship of Offset and Gain Adjustments for

VOUT = –10V to +10V Output Configuration. (Same

Theory Applies for VOUT = –5V to +5V.)

Digital Input

Input =

0000

Gain

Adjust

Rotates

the Line

1LSB

+ Full

Scale

– Full-Scale

(–V

REF OR –VREF/2)

Offset

Adjust

Translates

the Line

Input =

FFFF

Input = 8000

(+V

REF or +VREF/2)

When calibrating the DAC output, offset should be adjusted

first to avoid first order interaction of adjustments. In unipolar

mode, the DAC7731 offset is adjusted from code 0000H and

for either bipolar mode, offset adjustments are made at code

8000H. Gain adjustment can then be made at code FFFFH for

each configuration, where the output of the DAC should be

FIGURE 11. Generalized External Calibration Circuitry for

Gain and Symmetrical Offset Adjustment.

DAC7731

Optional Gain

Adjust

Optional Offset

Adjust

POT2

POT1

OADJ

(Other Connections Omitted

for Clarity)

–

OFFSET ADJUSTMENT

Offset adjustment is accomplished by introducing a small

current into the summing junction (SJ) of the DAC7731. The

voltage at SJ, or VSJ, is dependent on the output configura-

tion of the DAC7731. See Table IV for the required pin

strapping for a given configuration and the nominal values of

VSJ for each output range.

TABLE IV. Nominal VSJ versus VOUT and Reference Configu-

ration.

The current level required to adjust the DAC7731’s offset can

be created by using a potentiometer divider as shown in

Figure 11 Another alternative is to use a unipolar DAC in order

to apply a voltage, VOADJ, to the resistor RS. A ±2uA current

range applied to SJ will ensure offset adjustment coverage of

the

±0.1% maximum offset specification of the DAC7731.

When in a unipolar configuration (VSJ = 5V), only a single

resistor, RS, is needed for symmetrical offset adjustment with

a 0V to 10V VOADJ range. When in one of the two bipolar

configurations, VSJ is either +3.333V (±10V range) or +1.666V

(

±5V range), and circuit values chosen to match those given

in Table V will provide symmetrical offset adjust. Please refer

to Figure 11 for component configuration.

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