®

3

DAC7611

1

2

3

4

8

7

6

5

V

DD

CS

CLK

SDI

V

OUT

GND

CLR

LD

DAC7611

PIN CONFIGURATION

Top View

DIP

PIN CONFIGURATION

Top View

SOIC

VDD to GND .......................................................................... –0.3V to 6V

Digital Inputs to GND ............................................. –0.3V to VDD + 0.3V

VOUT to GND ........................................................... –0.3V to VDD + 0.3V

Power Dissipation ........................................................................ 325mW

Thermal Resistance,

θ

JA ............................................................ 150°C/W

Maximum Junction Temperature ................................................. +150

°C

Operating Temperature Range ...................................... –40

°C to +85°C

Storage Temperature Range ........................................ –65

°C to +150°C

Lead Temperature (soldering, 10s) ............................................. +300

°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS(1)

1

2

3

4

8

7

6

5

V

DD

CS

CLK

SDI

V

OUT

GND

CLR

LD

DAC7611

PIN DESCRIPTION

PIN

LABEL

DESCRIPTION

1VDD

Power Supply

2

CS

Chip Select (active LOW).

3

CLK

Synchronous Clock for the Serial Data Input.

4

SDI

Serial Data Input. Data is clocked into the internal

serial register on the rising edge of CLK.

5

LD

Loads the Internal DAC Register. NOTE: The DAC

register is a transparent latch and is transparent

when LD is LOW (regardless of the state of CS or

CLK).

6

CLR

Asynchronous Input to Clear the DAC Register.

When CLR is strobbed LOW, the DAC register is set

to 000H and the output voltage to 0V.

7

GND

Ground

8VOUT

Voltage Output. Fixed output voltage range of ap-

proximately 0V to 4.095V (1mV/LSB). The internal

reference maintains this output range over time,

temperature, and power supply variations (within

the values defined in the specifications section).

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

PACKAGE/ORDERING INFORMATION

MINIMUM

RELATIVE

DIFFERENTIAL

SPECIFICATION

PACKAGE

ACCURACY

NONLINEARITY

TEMPERATURE

DRAWING

ORDERING

TRANSPORT

PRODUCT

(LSB)

(LSB)

RANGE

PACKAGE

NUMBER(1)

NUMBER(2)

MEDIA

DAC7611P

±2

±1

–40

°C to +85°C

8-Pin DIP

006

DAC7611P

Rails

DAC7611U

±2

±1

–40

°C to +85°C

8-Lead SOIC

182

DAC7611U

Rails

""

"

"

""

DAC7611U/2K5

Tape and Reel

DAC7611PB

±1

±1

–40

°C to +85°C

8-Pin DIP

006

DAC7611PB

Rails

DAC7611UB

±1

±1

–40

°C to +85°C

8-Lead SOIC

182

DAC7611UB

Rails

""

"

"

""

DAC7611UB/2K5

Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are

available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7611/2K5” will get a single

2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.