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LTC2483 датащи(PDF) 13 Page - Linear Technology |
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LTC2483 датащи(HTML) 13 Page - Linear Technology |
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13 / 20 page ![]() LTC2450-1 13 24501fb APPLICATIONS INFORMATION 24501 F12 D15 D14 D13 D12 D2 D1 D0 SD0 clk1 clk2 clk3 clk4 clk15 clk16 clk17 SCK CONVERT CONVERT SLEEP DATA OUTPUT CS = LOW Figure 12. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example 24501 F13 D15 D14 D13 D12 D2 D1 D0 SD0 CS = LOW clk1 clk2 clk3 clk14 clk4 clk15 clk16 SCK CONVERT CONVERT DATA OUTPUT Figure 13. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example 2-Wire Operation The 2-wire operation modes, while reducing the number of required control signals, should be used only if the LTC2450-1 low power sleep capability is not required. In addition the option to abort serial data transfers is no longer available. Hardwire CS to GND for 2-wire operation. Figure 12 shows a 2-wire operation sequence which uses an idle-high (CPOL = 1) serial clock signal. The conversion status can be monitored at the SDO output. Following a conversion cycle, the ADC enters SLEEP state and the SDO output transitions from HIGH to LOW. Subsequently 16 clock pulses are applied to the SCK input in order to serially shift the 16 bit result. Finally, the 17th clock pulse is applied to the SCK input in order to trigger a new conversion cycle. Figure 13 shows a 2-wire operation sequence which uses an idle-low (CPOL = 0) serial clock signal. The conversion status cannot be monitored at the SDO output. Following a conversion cycle, the LTC2450-1 bypasses the SLEEP state and immediately enters the DATA OUTPUT state. At this moment the SDO pin outputs the most significant bit (D15) of the conversion result. The user must use external timing in order to determine the end of conversion and result availability. Subsequently 16 clock pulses are applied to SCK in order to serially shift the 16-bit result. The 16th clock falling edge triggers a new conversion cycle. PRESERVING THE CONVERTER ACCURACY The LTC2450-1 is designed to reduce as much as possible the conversion result sensitivity to device decoupling, PCB layout, antialiasing circuits, line and frequency perturbations. Nevertheless, in order to preserve the very high accuracy capability of this part, some simple precautions are desirable. |
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