VLSI
Solution
y
VS1103b
VS1103B
5. SPI BUSES
5 SPI Buses
5.1 General
The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1103b’s
Serial Data Interface SDI (Chapters 5.4 and 6.4) and Serial Control Interface SCI (Chapters 5.5 and 6.5).
5.2 SPI Bus Pin Descriptions
5.2.1 VS1002 Native Modes (New Mode)
These modes are active on VS1103b when SM SDINEW is set to 1 (default at startup). DCLK, SDATA
and BSYNC are replaced with GPIO2, GPIO3 and XDCS, respectively.
SDI Pin
SCI Pin
Description
XDCS
XCS
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. If SM SDISHARE is 1, pin
XDCS is not used, but the signal is generated internally by inverting
XCS.
SCK
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
SI
Serial input. If a chip select is active, SI is sampled on the rising CLK edge.
-
SO
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
5.2.2 VS1001 Compatibility Mode
This mode is active when SM SDINEW is set to 0. In this mode, DCLK, SDATA and BSYNC are active.
SDI Pin
SCI Pin
Description
-
XCS
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state.
BSYNC
-
SDI data is synchronized with a rising edge of BSYNC.
DCLK
SCK
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
SDATA
SI
Serial input. SI is sampled on the rising SCK edge, if XCS is low.
-
SO
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
Version 1.01, 2007-09-03
15
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