Data Sheet

LTM8060F

analog.com

Rev. A

32 of 44

Figure 67. Layout Showing Suggested External Components, GND Plane, and Thermal Vias

Hot-Plugging Safely

The small size, robustness, and low impedance of ceramic capacitors make them an attractive option for the input

bypass capacitor of LTM8060F. However, these capacitors can cause problems if the LTM8060F is plugged into a

live supply (Refer to the Application Note 88 for a complete discussion). The low-loss ceramic capacitor combined

with stray inductance in series with the power source forms an underdamped tank circuit, and the voltage at the

VINn pin of the LTM8060F can ring to more than twice the nominal input voltage, possibly exceeding the LTM8060F’s

rating and damaging the part. If the input supply is poorly controlled or the LTM8060F is hot-plugged into an

energized supply, the input network should be designed to prevent this overshoot. This can be accomplished by

installing a small resistor in series to VINn, but the most popular method of controlling input voltage overshoot is

adding an electrolytic bulk cap to the VINn net. This capacitor’s relatively high equivalent series resistance damps

the circuit and eliminates the voltage overshoot. The extra capacitor improves low-frequency ripple filtering and

can slightly improve the efficiency of the circuit, though it is likely to be the largest component in the circuit.

Thermal Considerations

The LTM8060F output current may need to be derated if it is required to operate in a high ambient temperature.

The amount of current derating is dependent upon the input voltage, output power, and ambient temperature.

The derating curves shown in the Typical Performance Characteristics section can be used as a guide. These curves

were generated by the LTM8060F mounted to a 104cm2 6-layer FR4 PCB. Boards of other sizes and layer counts can

exhibit different thermal behavior, so it is incumbent upon the user to verify proper operation over the intended

system’s line, load, and environmental operating conditions.

For increased accuracy and fidelity to the actual application, many designers use FEA or computational fluid

dynamics (CFD) to predict thermal performance. To that end, the pin configuration typically gives three dominant

thermal coefficients:

1. θJA – Thermal resistance from junction to ambient.

2. θJCbot – Thermal resistance from the junction to the bottom of the product case.

3. θJCtop – Thermal resistance from the junction to the top of the product case.

While the meaning of each of these coefficients may seem to be intuitive, JEDEC has defined each to avoid

confusion and inconsistency. These definitions are given in JESD5112 and are quoted or paraphrased as follows.

COUT2

COUT3

COUT1

COUT4

CIN1

CIN2

CIN34

CIN34

RT34

RT12