AMC80

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SBOS559B – MAY 2011 – REVISED OCTOBER 2015

7.5.3 Interrupt Mask Registers

Table 6. Interrupt Mask Register 1 (Address = 03h, Default = 00h)

BIT

NAME

TYPE

DESCRIPTION

0

CH0

R/W

1

CH1

R/W

2

CH2

R/W

3

CH3

R/W

'1' disables the corresponding interrupt status bit in Table 4 to trigger the INT interrupt.

4

CH4

R/W

5

CH5

R/W

6

CH6

R/W

7

INT_IN

R/W

Table 7. Interrupt Mask Register 2 (Address = 04h, Default = 00h)

BIT

NAME

TYPE

DESCRIPTION

0

Hot Temperature

R/W

1

BTI

R/W

2

FAN 1

R/W

'1' disables the corresponding interrupt status bit in Table 5 to trigger the INT interrupt.

3

FAN 2

R/W

4

GPI/CI

R/W

5

OS

R/W

INT Interrupt Mode

6

R/W

'0' selects Default Interrupt mode. '1' selects One-Time Interrupt mode.

Select

OS Interrupt Mode

7

R/W

'0' selects Comparator mode. '1' selects One-Time Interrupt mode.

Select

7.5.4 Fan Divisor/RST_OUT/OS Register

Table 8. Fan Divisor/RST_OUT/OS Register (Address = 05h, Default = 14h)

BIT

NAME

TYPE

DESCRIPTION

0

FAN1 Mode Select

R/W

'1' selects the level-sensitive input mode. '0' selects the fan count mode for the FAN1 input.

1

FAN2 Mode Select

R/W

'1' selects the level-sensitive input mode. '0' selects the fan count mode for the FAN2 input.

2

FAN1 RPM Control 1

R/W

FAN1 speed control:

'00' = divide by 1.

'01' = divide by 2.

'10' = divide by 4.

3

FAN1 RPM Control 0

R/W

'11' = divide by 8.

If level-sensitive input is selected, '01' selects an active-low input and '00' selects an active-

high input.

4

FAN2 RPM Control 1

R/W

FAN2 speed control:

'00' = divide by 1.

'01' = divide by 2.

'10' = divide by 4.

5

FAN2 RPM Control 0

R/W

'11' = divide by 8.

If level select input is selected, '01' selects an active-low input and '00' selects an active-high

input.

'1' enables OS mode on the RST_OUT/OS pin when bit 7 is set to '0'.

6

OS Pin Enable

R/W

NOTE: When bits 6 and 7 are both set to '1', the RST_OUT/OS pin is disabled.

'1' enables RST_OUT mode on the RST_OUT/OS pin when bit 6 is set to '0'.

7

RST_OUT Pin Enable

R/W

NOTE: When bits 6 and 7 are both set to '1', the RST_OUT/OS pin is disabled.

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