MP6527

– 40V, 0.8A MOTOR DRIVER WITH SERIAL INPUT CONTROL

MP6527 Rev. 1.0

MonolithicPower.com

12

9/23/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2021 MPS. All Rights Reserved.

OPERATION

The MP6527 is a 10-channel, half-bridge double-

DMOS

output

driver

with

integrated

power

MOSFETs.

The IC’s 10 half-bridges can be

controlled separately via a standard serial data

interface, and have various diagnostic functions.

Serial Interface

Data transfer starts with the falling edge signal of

the CS pin. Execution of new input data is enabled

on the rising edge of the CS signal. Data must

appear at the DI pin synchronized to the CLK pin,

and is accepted on the falling edge of the CLK

signal. For DI, the MSB (SRR, bit[15]) must be

transferred first. The last 16 bits clocked into DI

are transferred to the device’s data register if there

is no frame error. Otherwise, all DI data is ignored

and the previous input data is preserved.

The output data at the DO pin is enabled on the

falling edge of CS. In addition to the 16-bit status

data, a pseudo-bit (PRE_15) can also be retrieved

from

the

DO

output.

The

latched

thermal

shutdown (TSD) status bit (PRE_15) is available

on DO until the first rising CLK edge after CS goes

low. The output data changes their state with the

CLK rising edge, and remains stable until the next

CLK rising edge appears. When CS is high, DO is

in a tri-state condition.

The following conditions must be met for a valid

TSD read to be captured:

1. CLK and DI are low before the CS cycle begins.

2. CS transitions from high to low.

3. The CS set-up time is satisfied.

Figure 3 shows the SPI communication. Table 1

and Table 2 show the input control registers. Table

3 and Table 4 show the output diagnostic registers.

CS

DI

CLK

DO

DO

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PRE_15

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Figure 3: Data Transfer

Table 1: Input Control Registers (Channels 1 to 6, Input Bit[14] = 0)

Channels 1 to 6 (Input Bit[14] = 0)

Bit

Input Register

Function

15

SRR

Status register reset.

1: Reset, the error bits of the corresponding status register in the output data

register are set to low

0: Not reset, SRR is invalid

14

CH_SEL

This bit selects the channel group.

1: Half-bridge, bits[10:7]

0: Half-bridge, bits [6:1]

13

OLSD_EN

This bit enables open-load detection shutdown (OLD_SD) for half-bridge 1 (HB1)

to half-bridge 6 (HB6). This feature allows the affected output stage to switch off

if a true open-load or under-load condition is detected.

1: Enabled

0: Disabled

12

HBEN6

Enables half-bridge 6.

1: Half-bridge 6 is active

0: Half-bridge 6 is in Hi-Z