MP6530–5V TO 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER

MP6530 Rev. 1.13

www.MonolithicPower.com

9

8/9/2018

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© 2018 MPS. All Rights Reserved.

PIN FUNCTIONS

QFN

Pin #

TSSOP

Pin #

Name

Description

1

26

VIN

Input supply voltage. Bypass to ground with a ceramic capacitor. Additional

bulk capacitance may be required. See Applications Information section.

2

27

CPA

Charge pump capacitor. Connect a ceramic capacitor between these pins.

See Applications Information section.

3

28

CPB

4

1

VREG

Gate drive supply output. Connect a ceramic capacitor to ground.

See

Applications Information section.

5

2

BSTA

Bootstrap phase A. Connect a ceramic capacitor to SHA.

See Applications Information section.

6

3

SHA

High-side source connection phase A.

7

4

GHA

High-side gate drive phase A.

8

5

GLA

Low-side gate drive phase A.

9

6

BSTB

Bootstrap phase B. Connect a ceramic capacitor to SHB.

See Applications Information section.

10

7

SHB

High-side source connection phase B.

11

8

GHB

High-side gate drive phase B.

12

9

GLB

Low-side gate drive phase B.

13

10

BSTC

Bootstrap phase C. Connect a ceramic capacitor to SHC.

See Applications Information section.

14

11

SHC

High-side source connection phase C.

15

12

GHC

High-side gate drive phase C.

16

13

GLC

Low-side gate drive phase C.

17

14

LSS

Low-side Source Connection.

18

15

PWMC

PWM input pin for phase C. High drivers phase C high; low drivers phase C

low. Internal pulldown.

19

16

PWMB

PWM input pin for phase B. High drivers phase B high; low drivers phase B

low. Internal pulldown.

20

17

PWMA

PWM input pin for phase A. High drivers phase A high; low drivers phase A

low. Internal pulldown.

21

18

ENC

Enable pin for phase C. Active high enables the gate driver for phase C; low

disables the gate driver for phase C. Internal pulldown.

22

19

ENB

Enable pin for phase B. Active high enables the gate driver for phase B; low

disables the gate driver for phase B. Internal pulldown..

23

20

ENA

Enable pin for phase A. Active high enables the gate driver for phase A; low

disables the gate driver for phase A. Internal pulldown.

24

21

nFAULT

Fault indication. Open-drain output. nFAULT is logic low when in a fault

condition.

25

22

nSLEEP

Sleep mode input. Logic low to enter low-power sleep mode; high to enable.

Internal pulldown.

26

23

OCREF

Over-current protection reference voltage input.

27

24

DT

Dead time setting. Connect a resistor to ground to set the dead time. See

Applications Information section.

28

25

GND

Ground.