P240 datasheet(93/348 Pages) ALTERA

93 / 348 page

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

5–33

Spread-Spectrum Clocking

December 2011

Altera Corporation

Cyclone III Device Handbook

Volume 1

Figure 5–24 shows the dynamic phase shifting waveform.

The PHASESTEP signal is latched on the negative edge of SCANCLK (a,c) and must remain

asserted for at least two SCANCLK cycles. Deassert PHASESTEP after PHASEDONE goes low.

On the second SCANCLK rising edge (b,d) after PHASESTEP is latched, the values of

PHASEUPDOWN

and PHASECOUNTERSELECT are latched and the PLL starts dynamic

phase-shifting for the specified counters, and in the indicated direction. PHASEDONE is

deasserted synchronous to SCANCLK at the second rising edge (b,d) and remains low

until the PLL finishes dynamic phase-shifting. Depending on the VCO and SCANCLK

frequencies, PHASEDONE low time may be greater than or less than one SCANCLK cycle.

You can perform another dynamic phase-shift after the PHASEDONE signal goes from

low to high. Each PHASESTEP pulse enables one phase shift. PHASESTEP pulses must be

at least one SCANCLK cycle apart.

f For information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager, refer

to the Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction user

guide.

Spread-Spectrum Clocking

The Cyclone III device family can accept a spread-spectrum input with typical

modulation frequencies. However, the device cannot automatically detect that the

input is a spread-spectrum signal. Instead, the input signal looks like deterministic

jitter at the input of the PLL. Cyclone III device family PLLs can track a

spread-spectrum input clock as long as it is in the input jitter tolerance specifications

and the modulation frequency of the input clock is below the PLL bandwidth, which

is specified in the fitter report. The Cyclone III device family cannot generate

spread-spectrum signals internally.

PLL Specifications

f For information about PLL specifications, refer to the Cyclone III Device Data Sheet and

Cyclone III LS Device Data Sheet chapters.

Figure 5–24. Timing Diagram for Dynamic Phase Shift

PHASEDONE goes low

synchronous with SCANCLK

SCANCLK

PHASESTEP

PHASEUPDOWN

PHASECOUNTERSELECT

PHASEDONE

P240 датащи(PDF) 93 Page - Altera Corporation

P240 датащи(HTML) 93 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL