CDC319

1-LINE TO 10-LINE CLOCK DRIVER

WITH I2C CONTROL INTERFACE

SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001

6

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

switching characteristics over recommended operating conditions

PARAMETER

FROM

TO

TEST CONDITIONS

MIN

MAX

UNIT

A

Y

1.2

3.6

ns

tPLH

Low-to-high level propagation delay time

SCLOCK

↓

SDATA

valid

VCC = 3.3 V ±0.185 V,

See Figure 3

2

µs

tPLH

Low-to-high level propagation delay time

SDATA

↑

Y

VCC = 3.3 V ±0.185 V,

See Figure 3

150

ns

A

Y

1.2

3.6

ns

tPHL

High-to-low level propagation delay time

SCLOCK

↓

SDATA

valid

VCC = 3.3 V ±0.185 V,

See Figure 3

2

µs

tPHL

High-to-low level propagation delay time

SDATA

↑

Y

VCC = 3.3 V ±0.185 V,

See Figure 3

150

ns

tPZH

Enable time to the high level

tPZL

Enable time to the low level

OE

Y

1

47

ns

tPHZ

Disable time from the high level

OE

Y

1

4.7

ns

tPLZ

Disable time from the low level

tsk(o)

Skew time

A

Y

250

ps

tsk(p)

Skew time

A

Y

500

ps

tsk(pr)

Skew time

A

Y

1

ns

tr

Rise time

Y

0.5

1.3

ns

t

Rise time (see Note 4 and

SDATA

CL = 10 pF

6

ns

tr

(

Figure 3)

SDATA

CL = 400 pF

250

ns

tf

Fall time

Y

0.5

1.3

ns

tf

Fall time (see Note 4 and

SDATA

CL = 10 pF

20

ns

tf

(

Figure 3)

SDATA

CL = 400 pF

250

ns

CL = 30 pF, TA = 70°C

100

f

Operating frequency (see Note 5)

CL = 20 pF, TA = 70°C

125

MHz

CL = 15 pF, TA = 70°C

140

NOTES:

4. This parameter has a lower limit than BUS specification. This allows use of series resistors for current spike protection.

5. See Figure 4 (Frequency versus Capacitive Load).