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AVCC

AGND

CLKIN

SEL

OE

GND

1Y1

VCC

GND

1Y2

VCC

GND

1Y3

VCC

AVCC

AGND

FBIN

TEST

CLR

VCC

2Y1

GND

VCC

2Y2

GND

VCC

2Y3

GND

DB PACKAGE

(TOP VIEW)

DESCRIPTION

CDC2536

SCAS377E – APRIL 1994 – REVISED JULY 2004

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

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Low Output Skew for Clock-Distribution and

Clock-Generation Applications

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Operates at 3.3-V VCC

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Distributes One Clock Input to Six Outputs

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One Select Input Configures Three Outputs to

Operate at One-Half or Double the Input

Frequency

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No External RC Network Required

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On-Chip Series Damping Resistors

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External Feedback Pin (FBIN) Is Used to

Synchronize the Outputs to the Clock Input

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Application for Synchronous DRAM,

High-Speed Microprocessor

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TTL-Compatible Inputs and Outputs

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Outputs Drive 50-

Ω Parallel-Terminated

Transmission Lines

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State-of-the-Art EPIC-IIB™ BiCMOS Design

Significantly Reduces Power Dissipation

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Distributed VCC and Ground Pins Reduce

Switching Noise

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Packaged in Plastic 28-Pin Shrink

Small-Outline Package

The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to

precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is

specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from

50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536

operates at 3.3-V VCC and is designed to drive a 50-W transmission line. The CDC2536 also provides on-chip

series-damping resistors, eliminating the need for external termination components.

The feedback (FBIN) input is used to synchronize the output clocks in frequency and phase to the input clock

(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between

CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input

configures three Y outputs to operate at one-half or double the CLKIN frequency, depending on which pin is fed

back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty

cycle at the input clock.

Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.

When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass

the PLL. TEST should be strapped to GND for normal operation.

Unlike many products containing PLLs, the CDC2536 does not require external RC networks. The loop filter for

the PLL is included on-chip, minimizing component count, board space, and cost.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-IIB is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 1994–2004, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.