Data Sheet

ADRF5142

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 9 of 10

The ADRF5142 has two power supply pins (VDD and VSS) and

one control pin (CTRL). Figure 13 shows the external components

and connections for the supply and control pins. The VDD pin is

decoupled with 100 pF and 100 nF multilayer ceramic capacitors.

The VSS and control pins are decoupled with 100 pF multilayer

ceramic capacitors. The device pinout allows the placement of

the decoupling capacitors close to the device. No other external

components are needed for bias and operation, except DC-blocking

capacitors on the RF pins when the RF lines are biased at a voltage

different than 0 V. For more details, see the Pin Configuration and

Function Descriptions section.

Figure 13. Recommended Schematic

RECOMMENDATIONS FOR PCB DESIGN

The RF ports are matched to 50 Ω internally, and the pinout is

designed to mate a coplanar waveguide (CPWG) with a 50 Ω char-

acteristic impedance on the PCB. Figure 14 shows the referenced

CPWG RF trace design for an RF substrate with 8 mil thick Rogers

RO4003 dielectric material. An RF trace with 14 mil width and 7 mil

clearance is recommended for 1.5 mil finished copper thickness.

Figure 14. Example PCB Stack Up

Figure 15 shows the routing of the RF traces, supply, and control

signals from the device. The ground planes are connected with as

many filled as allowed through vias for optimal RF and thermal

performance. The primary thermal path for the device is the bottom

side, and therefore, a heatsink is required under the PCB to ensure

maximum heat dissipation and to reduce thermal rise on the PCB

during high-power applications.

Figure 15. PCB Routings

Figure 16 shows the recommended layout from the device RF

pins to the 50 Ω CPWG on the referenced stackup. PCB pads

are drawn 1:1 to device pads. The ground pads are drawn as

soldermask defined. The signal pads are drawn as pad defined.

The RF trace from the PCB pad is extended with the same width

up to the package edge and tapered to an RF trace with a 45°

angle. The paste mask is also designed to match the pad without

any aperture reduction. The paste is divided into multiple openings

for the paddle.

Figure 16. Recommended RF Pin Transitions

For further recommendations and alternate PCB stackups with

different dielectric thickness and CPWG design, contact Analog

Devices, Inc., Technical Support Request.