TMP400 datasheet(13/25 Pages) TI

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CONSECUTIVE ALERT REGISTER

SERIAL INTERFACE

SERIAL BUS ADDRESS

BUS OVERVIEW

READ/WRITE OPERATIONS

TMP400

SBOS404 – DECEMBER 2007

The value in the Consecutive Alert Register (address

The TMP400 operates only as a slave device on

22h) determines how many consecutive out-of-limit

either the Two-Wire bus or the SMBus. Connections

measurements

must

occur

measurement

to either bus are made via the open-drain I/O lines,

channel before the ALERT signal is activated. The

SDA, and SCL. The SDA and SCL pins feature

value in this register does not affect bits in the Status

integrated spike suppression filters and Schmitt

Values

one,

two,

three,

four

triggers to minimize the effects of input spikes and

consecutive

conversions

can

selected;

one

bus noise. The TMP400 supports the transmission

conversion

the

default.

This

function

allows

protocol for fast (1kHz to 400kHz) and high-speed

additional filtering for the ALERT pin. The consecutive

(1kHz

3.4MHz)

modes.

All

data

bytes

are

alert bits are shown in Table 8.

transmitted MSB first.

Table 8. Consecutive Alert Register

CONSECUTIVE ALERT REGISTER

To communicate with the TMP400, the master must

(READ = 22h, WRITE = 22h, POR = 01h)

first address slave devices via a slave address byte.

NUMBER OF CONSECUTIVE

The slave address byte consists of seven address

OUT-OF-LIMIT

bits, and a direction bit indicating the intent of

MEASUREMENTS

executing a read or write operation. The address of

the TMP400 is set by the A0 and A1 pins. TMP400

addresses

and

corresponding

and

configurations are shown in Table 9.

Table 9. Device Addresses

(1) Note that bit 7 of the Consecutive Alert Register controls the

ADDRESS

enable/disable of the timeout function. See the Timeout

Function section for a description of this feature.

GND

0011 000

GND

High-Z

0011 001

GND

VCC

0011 010

The TMP400 is SMBus interface-compatible. In

High-Z

GND

0101 001

SMBus protocol, the device that initiates the transfer

High-Z

0101 010

is called a master, and the devices controlled by the

High-Z

VCC

0101 011

master are slaves. The bus must be controlled by a

VCC

GND

1001 100

master device that generates the serial clock (SCL),

controls the bus access, and generates the START

VCC

High-Z

1001 101

and STOP conditions.

VCC

1001 110

To address a specific device, a START condition is

initiated. START is indicated by pulling the data line

(SDA) from a high to low logic level while SCL is

Accessing a particular register on the TMP400 is

high. All slaves on the bus shift in the slave address

accomplished by writing the appropriate value to the

byte, with the last bit indicating whether a read or

Pointer Register. The value for the Pointer Register is

write operation is intended. During the ninth clock

the first byte transferred after the slave address byte

pulse, the slave being addressed responds to the

with the R/W bit low. Every write operation to the

master by generating an Acknowledge and pulling

TMP400 requires a value for the Pointer Register

SDA low.

(see Figure 14).

Data transfer is then initiated and sent over eight

When reading from the TMP400, the last value stored

clock pulses followed by an Acknowledge bit. During

in the Pointer Register by a write operation is used to

data transfer, SDA must remain stable while SCL is

determine which register is read by a read operation.

high, because any change in SDA while SCL is high

To change the register pointer for a read operation, a

is interpreted as a control signal.

new value must be written to the Pointer Register.

Once all data have been transferred, the master

This transaction is accomplished by issuing a slave

generates a STOP condition. STOP is indicated by

address byte with the R/W bit low, followed by the

pulling SDA from low to high, while SCL is high.

Pointer

byte.

additional

data

are

required. The master can then generate a START

condition and send the slave address byte with the

R/W bit high to initiate the read command. See

Figure 16 for details of this sequence. If repeated

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