6

Test Circuits and Waveforms

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

FIGURE 3. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 4. HC SETUP TIMES, HOLD TIMES, REMOVAL

TIME, AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

CLOCK

90%

50%

10%

GND

VCC

trCL

tfCL

50%

50%

tWL

tWH

10%

tWL + tWH =

fCL

I

tPHL

tPLH

tTHL

tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns

tf = 6ns

90%

trCL

tfCL

GND

VCC

GND

VCC

50%

90%

10%

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

VCC

50%

50%

90%

10%

50%

90%

tREM

tPLH

tSU(H)

tTLH

tTHL

tH(L)

tPHL

IC

CL

50pF

tSU(L)

tH(H)

CD54HC4059, CD74HC4059

CD54HC4059, CD74HC4059