CD74HC138-Q1

HIGH-SPEED CMOS LOGIC

3- TO 8-LINE INVERTING DECODER/DEMULTIPLEXER

SCLS580A − APRIL 2004 − REVISED APRIL 2008

2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

FUNCTION TABLE

ENABLE INPUTS

SELECT INPUTS

OUTPUTS

E3

E2

E1

A2

A1

A0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

X

X

H

X

X

X

H

H

H

H

H

H

H

H

L

XX

X

XX

H

HH

HH

HH

H

X

HX

X

XX

H

HH

HH

HH

H

H

LL

L

LL

L

HH

HH

HH

H

H

LL

L

LH

H

L

H

HH

HH

H

H

LL

L

HLH

H

L

HH

HH

H

H

LL

L

HH

H

HH

L

H

HH

H

H

LL

H

LL

H

HH

H

L

HH

H

H

LL

H

LH

H

HH

HH

L

H

H

H

LL

H

HLH

HH

HH

H

L

H

H

L

L

H

H

H

H

H

H

H

H

H

H

L

NOTE: H = High voltage level, L = Low voltage level, X = Don’t care

logic diagram (positive logic)

E3

E2

E1

A2

A1

A0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Data

Outputs

Select

Inputs

Enable

Inputs

1

2

3

4

5

6

15

14

13

12

11

10

9

7