CD74FCT843A

BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCBS727 – JULY 2000

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D BiCMOS Technology With Low Quiescent

Power

D Buffered Inputs

D Noninverted Outputs

D Input/Output Isolation From VCC

D Controlled Output Edge Rates

D 48-mA Output Sink Current

D Output Voltage Swing Limited to 3.7 V

D SCR Latch-Up-Resistant BiCMOS Process

and Circuit Design

D Packaged in Plastic Small-Outline Package

description

The CD74FCT843A is a 9-bit, bus-interface,

D-type latch with 3-state outputs, designed

specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for

implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS

transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing

(0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC

bounce and ground bounce and their effects during simultaneous output switching. The output configuration

also enhances switching speed and is capable of sinking 48 mA.

The CD74FCT843A outputs are transparent to the inputs when the latch-enable (LE) input is high. The latches

are transparent D-type latches. When LE goes low, the data is latched. The output-enable (OE) input controls

the 3-state outputs. When OE is high, the outputs are in the high-impedance state. The latch operation is

independent of the state of the output enable. This device, having preset (PRE) and clear (CLR), are ideal for

parity-bus interfacing. When PRE is low, the outputs are high if OE is low. PRE overrides CLR. When CLR is

low, the outputs are low if OE is low. When CLR is high, data can be entered into the latch. The device provides

noninverted outputs.

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can

be entered while the outputs are in the high-impedance state.

The CD74FCT843A is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

(each latch)

INPUTS

OUTPUT

PRE

CLR

OE

LE

D

Q

L

X

L

X

X

H

H

LL

X

X

L

H

HL

HL

L

H

HL

H

H

H

H

HL

L

X

Q0

X

X

H

X

X

Z

Copyright

© 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

M PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

OE

1D

2D

3D

4D

5D

6D

7D

8D

9D

CLR

GND

VCC

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

9Q

PRE

LE