CD74ACT297

DIGITAL PHASE-LOCKED LOOP

SCHS297D – AUGUST 1998 – REVISED JUNE 2002

9

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

tPLH

tPHL

tPLH

tPHL

φB

φA1

XORPD OUT

50% VCC

1.5 V

50% VCC

50% VCC

50% VCC

1.5 V

1.5 V

1.5 V

3 V

0 V

3 V

0 V

VOL

≈VCC

Figure 8. Phase Input (

φB, φA2) to Output (XORPD OUT) Propagation Delays

φB

φA2

ECPD OUT

tPHL

tPLH

3 V

0 V

VOL

≈VCC

50% VCC

1.5 V

50% VCC

1.5 V

1.5 V

3 V

0 V

Figure 9. Phase Input (

φB, φA2) to Output (ECPD OUT) Propagation Delays

D/U

ENCTR

K CLK

1/fmax

tsu

tw

tsu

tH

tH

NOTE A: Shaded areas indicate when the input is permitted to change for predictable output performance.

3 V

0 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

3 V

0 V

(See Note A)

Figure 10. Clock (K CLK) Pulse Duration and Maximum Clock-Pulse Frequency,

and Inputs (D/U, ENCTR) to Clock (K CLK) Setup and Hold Times