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L6740LTR датащи(PDF) 40 Page - STMicroelectronics

номер детали L6740LTR
подробное описание детали  Hybrid controller (41) for AMD SVID and PVID processors
PDF  44 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6740LTR датащи(HTML) 40 Page - STMicroelectronics

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LTB technology™
L6740L
40/44
●
Gain Design. Through the LTBGAIN pin it is possible to modify the slope of the LTB
Ramp in order to modulate the entity of the LTB response once the LT has been
detected. In fact, the response depends on the board design and its parasitics requiring
different actions from the controller.
Leaving the LTBGAIN pin floating, the maximum pulse-width is programmed. The slope
of the LTB ramp will be equal to 1/2 of the OSC ramp slope.
Connecting RLTBGAIN to GND, the LTB Ramp slope can be modified as follow:
Where ILTBGAIN is the current sunk from LTBGAIN pin and IOSC is the OSC current
(20
µA plus the current sunk from the OSC pin).
LTB TechnologyTM Design Tips.
–
Decrease RLTB to increase the system sensitivity making the system sensitive to
smaller dVOUT.
–
Increase CLTB to increase the system sensitivity making the system sensitive to
higher dV/dt.
–
Increase RLTBGAIN to increase the width of the LTB pulse reducing the system
ring-back.
LTBRamp
Slope
OSC
Slope
1
I
LTBGAIN
I
OSC
------------------------
+
⎝⎠
⎛⎞
⋅
=



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