L6740L datasheet(25/44 Pages) STMICROELECTRONICS

25 / 44 page

L6740L

Output voltage positioning

25/44

Figure 10.

Current reading - CORE section (left) and NB section (right)

The current read through the CSx+ / CSx- pairs is converted into a current IINFOx propor-

tional to the current delivered by each phase and the information about the average current

IAVG = ΣIINFOx / N is internally built into the device (N is the number of working phases). The

error between the read current IINFOx and the reference IAVG is then converted into a voltage

that with a proper gain is used to adjust the duty cycle whose dominant value is set by the

voltage error amplifier in order to equalize the current carried by each phase.

6.3

CORE section - Load-line and load-indicator (Optional)

L6740L is able to introduce a dependence of the output voltage on the load current recover-

ing part of the drop due to the output capacitor ESR in the load transient. Introducing a

dependence of the output voltage on the load current, a static error, proportional to the out-

put current, causes the output voltage to vary according to the sensed current.

Figure 10 shows the Current Sense Circuit used to implement the Load-Line. The current

flowing across the inductor(s) is read through the R - C filter across CSx+ and CSx- pins. RG

programs a transconductance gain and generates a current ICSx proportional to the current

of the phase. The sum of the ICSx current is then sourced by the FB pin (IDROOP). RFB gives

the final gain to program the desired load-line slope (Figure 9).

Time constant matching between the inductor (L / DCR) and the current reading filter (RC)

is required to implement a real equivalent output impedance of the system so avoiding over

and/or under shoot of the output voltage as a consequence of a load transient. See

Section 6.2. The output characteristic vs. load current is then given by (Offset disabled):

Where RLL is the resulting load-line resistance implemented by the CORE Section.

The whole power supply can be then represented by a “real” voltage generator with an

equivalent output resistance RLL and a voltage value of VID.

RFB resistor can be then designed according to the RLL specifications as follow:

Caution:

Load-Line (DROOP) implementation is optional, in case it is not desired, the resulting cur-

rent information may be employed for other purposes, such as an additional Load Indicator

CSx+

CSx-

DCRx

RISEN

PHASEx

NB Current Sense across LS Mosfet

VDD Inductor DCR Current Sense

INB_ISEN

ICSx-=IINFOx

From

ext Driver

OUT

CORE

VID

DROOP

⋅

–

VID

DCR

------------- I

OUT

⋅⋅

–

VID

OUT

⋅

–

DCR

-------------

⋅

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