ST10F272M datasheet(150/175 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F272M

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24.8.13

External clock drive XTAL1

When Direct Drive configuration is selected during reset, it is possible to drive the CPU clock

directly from the XTAL1 pin, without particular restrictions on the maximum frequency, since

the on-chip oscillator amplifier is bypassed. The speed limit is imposed by internal logic that

targets a maximum CPU frequency of 40 MHz.

In all other clock configurations (Direct Drive with Prescaler or PLL usage) the on-chip

oscillator amplifier is not bypassed, so it determines the input clock speed limit. Then, when

the on-chip oscillator is enabled it is forbidden to use any external clock source different

from crystal or ceramic resonator.

Figure 49.

External clock drive XTAL1

Note:

When Direct Drive is selected, an external clock source can be used to drive XTAL1. The

maximum frequency of the external clock source depends on the duty cycle: When 40 MHz

is used, 50% duty cycle is granted (low phase = high phase = 12.5ns); when for instance

20 MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again

equal to 12.5ns).

24.8.14

Memory cycle variables

The tables below use three variables which are derived from the BUSCONx registers and

represent the special characteristics of the programmed memory cycle. The following table

describes how these variables are to be computed.

Table 68.

External clock drive

Parameter

Symbol

Direct drive

fCPU = fXTAL

Direct drive with

prescaler

fCPU = fXTAL / 2

PLL usage

fCPU = fXTAL x F

Unit

MinMax

Min

Max

XTAL1 period(1)(2)

The minimum value for the XTAL1 signal period is considered the theoretical minimum. The real minimum

value depends on the duty cycle of the input clock signal.

4 to 8 MHz is the input frequency range when using an external clock source. 40 MHz can be applied with

an external clock source only when Direct Drive mode is selected: in this case, the oscillator amplifier is

bypassed so it does not limit the input frequency.

tOSC SR

–

83.3

250

83.3

250

High time(3)

The input clock signal must reach the defined levels VIL2 and VIH2.

–3–

6–

Low time(3)

–3–

6–

Rise time(3)

–

2–2

–2

Fall time(3)

–

2–2

–2

VIL2

tOSC

VIH2

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