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About the Processor

Cortex-M3 is a low-power processor that features low gate count, low interrupt latency,

and low-cost debug. It is intended for deeply embedded applications that require FIQ

interrupt response features.

The Cortex-M3 processor includes:

A processor core

A Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor

core to achieve low latency interrupt processing

Multiple high-performance bus interfaces

A low-cost debug solution with the optional ability to:

— Implement breakpoints and code patches

— Implement watchpoints, tracing, and system profiling

— Support printf style debugging

— Bridge to a Trace Port Analyzer (TPA)

An optional Memory Protection Unit (MPU)

An optional Embedded Trace Macrocell (ETM) that enables reconstruction

of program execution

Interfaces

The processor has the following external interfaces:

Multiple memory and device bus interfaces

ETM interface

Trace port interface

Debug port interface

If the implementation includes an ETM, a Cross Trigger Interface (CTI)